PSRAM refresh / burst suspend

roman01
Posts: 1
Joined: Mon Sep 16, 2019 9:30 am

PSRAM refresh / burst suspend

Postby roman01 » Mon Sep 16, 2019 10:12 am

Hi,
We would like to use PSRAM32 or PSRAM64 hardware multiplexed: writing to PSRAM by an another controller, reading by ESP32 after multiplexing/switching the SPI lines.
Our writing would be performed in continuous bursts in QPI mode - that is sending data in as: command, address, data....
However our data is relatively large (crossing page boundaries, so CLK below 80 MHz), furthermore there will be "gaps" during which writing should be suspended for a certain period. Although this suspension can be achieved by pulling CE# high, this would terminate write command and we would need to re-submit new command and to calculate continuation address before sending new data. This seems to be not very practical for us because the gaps can be of various length, some very short - only several clocks, some long - a few thousand clock cycles. Simpler possibility would be to suspend the clock during the gap (effectively masking it by a "DATA_VALID" signal), however we are not sure if we would not screw-up internal memory refresh and/or break internal collision avoidance mechanism - there is not to much info in official PSRAM32/64 documentation about it, the only mention is that CE# should be pulled up immediately after a command. If so, what could be the timing - maximum "gaps" (no clock) without screwing-up internal refresh?

ESP_Sprite
Posts: 2832
Joined: Thu Nov 26, 2015 4:08 am

Re: PSRAM refresh / burst suspend

Postby ESP_Sprite » Tue Sep 17, 2019 3:08 am

The data you're looking for is in the 'Read/Write Timing' table. On the PSRAM64, to do refresh correctly, /CS should be made inactive at least once every 8 uS, and should stay inactive for 50 ns. Aside from that, as far as I can tell, clock timings do not matter and you can stop the clock if needed.

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