Reducing clock frequency

berpast
Posts: 4
Joined: Mon Feb 06, 2017 11:26 am

Reducing clock frequency

Postby berpast » Sun Feb 26, 2017 10:56 pm

In order to reduce the power consumption, while still retaining WiFi connections, I cannot use deep sleep mode.
For this reason I'm trying to reduce the frequency to 2MHz.

The frequency gets properly reduces by calling the function rtc_set_cpu_freq and properly scaling the variable _xt_tick_divisor in order to generate timer interrupts with the proper frequency (I had to modify portasm.h in order to use _xt_tick_divisor instead of the XT_TICK_DIVISOR macro).

But I'm having issues with WiFi: after sleeping for some time calling vTaskDelay, WiFi gets disconneted. I can see in the log the message:
"wifi: bcn_timout,ap_probe_send_start"

This message is not printed if I sleep without reducing the frequency before the sleep and increasing it at the end.

Do I have to adjust some wifi parameter in order to have the wifi properly react to the frequency reduction?

I know that the ESP team is working to a stable solution for frequency scaling, but some help would be really appreciated.

ESP_igrr
Posts: 834
Joined: Tue Dec 01, 2015 8:37 am

Re: Reducing clock frequency

Postby ESP_igrr » Mon Feb 27, 2017 12:43 am

WiFi peripheral needs BBPLL to be enabled, but the aforementioned CPU frequency change function will disable it once you go to XTAL_FREQ or lower.
Solution for this is to add a call which would allow frequency to be lowered, and another one to request 80MHz APB frequency, to the wifi modem sleep state machine. This part of code isn't open source, so I don't see a trivial way for you to achieve this.
I'm working on pretty much the same thing here; there are a few issues with timers drifting away due to many clock changes, I hope to solve them this week.

berpast
Posts: 4
Joined: Mon Feb 06, 2017 11:26 am

Re: Reducing clock frequency

Postby berpast » Sun Mar 12, 2017 10:53 am

I just pulled the latest idf and I'm unable to find any new code that would allow to reduce the frequency.
I don't want to pressure the dev team, but is there any update plan for the development of this item?

hwmaier
Posts: 26
Joined: Sun May 28, 2017 7:30 am

Re: Reducing clock frequency

Postby hwmaier » Tue Jun 13, 2017 11:32 pm

Following conversation above, does the Wifi and BT subsystems depend on APB clock to be 80MHz or can APB clock be changed to a different value without affecting Wifi & BT?

ESP_igrr
Posts: 834
Joined: Tue Dec 01, 2015 8:37 am

Re: Reducing clock frequency

Postby ESP_igrr » Wed Jun 14, 2017 12:24 am

berplast: clock frequency switching has been delayed to the next release. We plan to work on it along with light sleep.

hwmaier: WiFi and BT do require 80MHz APB clock to operate.

hwmaier
Posts: 26
Joined: Sun May 28, 2017 7:30 am

Re: Reducing clock frequency

Postby hwmaier » Wed Jun 14, 2017 1:05 am

@ESP_igrr: I thought that would be the case. Thank you for clarification. I was hoping to be able to reduce the APB_CLK so the CAN controller can run on a lower clock frequency so we can support certain standard baudrates. Seems I have run out of options now (refer to viewtopic.php?f=12&t=2142).

gatisp
Posts: 14
Joined: Thu May 26, 2016 11:49 am

Re: Reducing clock frequency

Postby gatisp » Tue Sep 26, 2017 7:09 pm

It seems that changing the cpu freq to 2Mhz using the rtc_clk_cpu_freq_set does not work now.

Using the simple app:

#include "esp_system.h"
#include "soc/rtc.h"
#include "rom/uart.h"

void app_main(void) {
printf("before freq set\n");
uart_tx_wait_idle(0);
rtc_clk_cpu_freq_set(RTC_CPU_FREQ_2M);
// rtc_clk_cpu_freq_set(RTC_CPU_FREQ_80M);
// rtc_clk_cpu_freq_set(RTC_CPU_FREQ_160M);
// rtc_clk_cpu_freq_set(RTC_CPU_FREQ_240M);
printf("after freq set\n");
}


The ESP32 board does not output anything after "before freq set" line.

Using sdk: 7d436c9a44b7506c3de4d5ed6decff8f35f64b67
Toolchain: xtensa-esp32-elf-cc (crosstool-NG crosstool-ng-1.22.0-73-ge28a011) 5.2.0


Is the 2Mhz mode supposed to work?

I am interested in Wifi sta mode + power save + light sleep / 2Mhz mode too. I would highly appreciate update on status of this. Thank you.
Attachments
sdkconfig.txt
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ESP_igrr
Posts: 834
Joined: Tue Dec 01, 2015 8:37 am

Re: Reducing clock frequency

Postby ESP_igrr » Tue Sep 26, 2017 10:06 pm

In your example, APB frequency has changed to 2MHz, but UART divider is still configured for 80MHz frequency. That might explain why you are not seeing any output.

With regards to the status of frequency switching, we are still working on this.

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