[IDFGH-2892] Endless SPI w/ DMA receive problem

NiclasH
Posts: 2
Joined: Mon Dec 28, 2015 4:34 am

[IDFGH-2892] Endless SPI w/ DMA receive problem

Postby NiclasH » Sun Mar 15, 2020 1:01 pm

Hi,
This issue is driving me bonkers.

I am reading an ADC128S102 (A/D converter) in endless mode. So, I set up VSPI with a descriptor to point back to itself, syncing up a CS via MCPWM Timer1 (should not be needed, but primarily to get stable oscilloscope readings).

The data that is sent out is very straight forward, "Next channel" is sent in bit3, bit4 and bit5 and meanwhile MISO is clocking in the "current channel". So, the out buffer is set up in this manner;
1. Allocate a DMA capable memory for the descriptor.
2. Clear all bits
3. 20 bytes, 16 bytes for the 8 channel addresses and then 4 bytes of "sync" where the CS (via timer) is pulled high.
4. no eof and next buffer is "myself"
5. Set up the channels to be read.
6. 255 in the 4 bytes so that they are easy to locate on the scope.

Code: Select all

   out = static_cast<lldesc_t *>(heap_caps_malloc(sizeof(lldesc_t), MALLOC_CAP_DMA));

   memset((void *) out, 0, sizeof(lldesc_t));
   out->size = 20;
   out->length = 20;
   out->offset = 0;
   out->sosf = 0;
   out->eof = 0;
   out->owner = 1;
   out->qe.stqe_next = out;
   out->buf = static_cast<uint8_t *>(heap_caps_malloc(20, MALLOC_CAP_DMA));
   out->buf[0] = 1 << 3;
   out->buf[1] = 0;
   out->buf[2] = 2 << 3;
   out->buf[3] = 0;
   out->buf[4] = 3 << 3;
   out->buf[5] = 0;
   out->buf[6] = 4 << 3;
   out->buf[7] = 0;
   out->buf[8] = 5 << 3;
   out->buf[9] = 0;
   out->buf[10] = 6 << 3;
   out->buf[11] = 0;
   out->buf[12] = 7 << 3;
   out->buf[13] = 0;
   out->buf[14] = 0 << 3;
   out->buf[15] = 0;
   out->buf[16] = 255;
   out->buf[17] = 255;
   out->buf[18] = 255;
   out->buf[19] = 255;
This works well, and I do the same in the DAC without issue.

Reading descriptor is set up in a similar fashion;

Code: Select all

   in = static_cast<lldesc_t *>(heap_caps_malloc(sizeof(lldesc_t), MALLOC_CAP_DMA));
   memset((void *) in, 0, sizeof(lldesc_t));
   in->size = 20;
   in->length = 20;
   in->offset = 0;
   in->sosf = 0;
   in->eof = 0;
   in->owner = 1;
   in->qe.stqe_next = in;
   in->buf = static_cast<uint8_t *>(heap_caps_malloc(20, MALLOC_CAP_DMA));
Then there is a bunch of code to set up DMA and SPI peripherals, as well as phasing the timer into exact clock. The SPI is running on 10MHz and the Timer is at 20MHz so I can adjust half phase of the CS vs SCLK


Now, On the oscilloscope, every single bit looks fine. I have checked all timing I can think of, with the scope. It all looks good externally.

HOWEVER, the buffer that is filled is having 2 major problems;

1. It starts off with the 5th value in the beginning of the in-buffer. Then 6th, 7th, 8th, followed by the 4 bytes reading during the CS-HIGH, then comes 1st, 2nd, 3rd and finally 4th value in the buffer. The 65534 is also a bit mysterious, and could be a clue.
Ex (16 bit values in buffer order); 1, 0, 0, 0, 65535, 65534, 1717, 1720, 858, 1717

2. After some time (minutes) everything in the in-buffer looks like mad, but there is no difference on the scope.
Ex; 768, 256, 0, 3, 65535, 65030, 46598, 47363, 23046, 46336
It definitely looks like "a byte off"

3. Then some more time later, we are "back", but we are now another byte off;
Ex; 1, 0, 0, 65535, 65534, 1719, 1722, 857, 1717, 2


So, my questions to Espressif engineers and anyone with DEEP understanding of how this works;

1. How can the READ function start (in relation to the WRITE operations) in the "wrong place"?

2. How can the descriptor sequence "lose" a byte and continue to do so every so seldom (but detrimentally in my application)?


Attached are scope photos, one for close up on start of descriptor, one at the "end" where the 255s are written out and one that shows a complete loop.
Pink/top = MISO
Cyan/2nd = SCLK
Yellow/ 3rd = MOSI
Blue / bottom = CS

Thanks in Advance
Niclas
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xiaoxufeng
Posts: 17
Joined: Mon Aug 28, 2017 10:25 am

Re: Endless SPI w/ DMA receive problem

Postby xiaoxufeng » Mon Mar 23, 2020 2:19 am

Hi NiclasH,

Could you explain how each signals are controlled? for example

CS: by SPI_MASTER or PWM
CLK: by SPI_MASTER or PWM

and do you use SPI_MASTER or SPI_SLAVE?

As far as I know, our SPI_MASTER doesn't provide any feature to "sync" the CS with an signal. It's always triggered by the SW. For SPI_SLAVE, it can respond to the CS signal, but there are quite a few timing and DMA controll issue to solve.

ESP_Alvin
Posts: 89
Joined: Thu May 17, 2018 2:26 am

Re: [IDFGH-2892] Endless SPI w/ DMA receive problem

Postby ESP_Alvin » Mon Mar 23, 2020 3:32 am

Moderator's note: update the topic title for issue tracking. Thanks.

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