Confused over IO_MUX_PIN_CTRL

Kaisha
Posts: 42
Joined: Thu Mar 05, 2020 8:59 pm

Confused over IO_MUX_PIN_CTRL

Postby Kaisha » Wed Sep 22, 2021 12:05 am

In the ESP32 TRM (page 70) there is the description for the IO_MUX_PIN_CTRL register. It clearly has something to do with routing the I2S clock signals to CLK_OUT1, CLK_OUT2, and CLK_OUT3special functions via the io mux.

1st, I'm not sure what the point of this register is. Since the I2S signals all have to be routed through the GPIO matrix anyways, under what circumstances would I want to route the clock directly through the io mux and not just use the GPIO matrix like every other signal?

2nd, the description is... bizzare:
If you want to output clock for I2S0 to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0x0;
CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0.
If you want to output clock for I2S1 to:
CLK_OUT1, then set PIN_CTRL[3:0] = 0xF;
CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0;
CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0. (R/W)

Note:
Only the above mentioned combinations of clock source and clock output pins are possible.
The default value of the register is all 0's, so as far as I can tell this leaves two options: 0x00000000 and 0x0000000F. So this means either I2S0 or I2S1 gets mapped to CLK_OUT1, CLK_OUT2, and CLK_OUT3, but no other combination? Why the cryptic description and not just state that there are two options? Am I missing something here?

ESP_Sprite
Posts: 8921
Joined: Thu Nov 26, 2015 4:08 am

Re: Confused over IO_MUX_PIN_CTRL

Postby ESP_Sprite » Wed Sep 22, 2021 12:40 am

I think the intention here is to allow for a MCLK. Some i2S codecs need this, and it's usually a pretty high clock, like 256*BCLK. Agree that it's really unclear from the TRM; I'll create an issue to clarify this.

WiFive
Posts: 3529
Joined: Tue Dec 01, 2015 7:35 am

Re: Confused over IO_MUX_PIN_CTRL

Postby WiFive » Wed Sep 22, 2021 7:49 am

viewtopic.php?t=1585

CLK_OUT1 = bits 0-3
CLK_OUT2 = bits 4-7
CLK_OUT3 = bits 8-11

Possible values

0 = i2s0
6 = apll
8 = apb
13 = cpu
15 = i2s1
other unknown values
Last edited by WiFive on Wed Sep 22, 2021 1:23 pm, edited 1 time in total.

Kaisha
Posts: 42
Joined: Thu Mar 05, 2020 8:59 pm

Re: Confused over IO_MUX_PIN_CTRL

Postby Kaisha » Wed Sep 22, 2021 11:46 am

That's certainly interesting (and makes more sense than what the TRM states), but where are you getting those values from?

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