What would you like to see in The Next Chip?

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Re: What would you like to see in The Next Chip?

Postby ESP_Sprite » Wed Jun 03, 2020 8:15 am

PHY's likely not going to happen, given the process requirements likely are pretty different from the rest of the chip; I don't think we can integrate the two on one silicon die easily.

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Re: What would you like to see in The Next Chip?

Postby Hackswell » Thu Jun 04, 2020 6:18 pm

I'm just a beginner with embedded controllers, and my interest is more in the devkit rather than the actual "chips", but here are a few items I've thought of:

* [esp32] Totally agree with more DMA accessible RAM that others have said. As attached displays and streaming are growing more and more, you can't have enough DMA RAM!
* [esp32] Everyone seems to be talking "extras" of the ~~CAN~~ TWAI, I2S, etc. Would more pins on the package be an option instead of muxing even more into the same number of pins? Pins could be placed closer, or even "bonus" pins on bottom. On a devkit, do something like the Teensy 4.0, where there are PLENTY of pins for general use, but for those with insane amount of peripherals, extra pads on the bottom or some such?
* [esp32] Better separation of church and steak? Reading around it seems that certain HW only runs on core0 or core1. I've seen users getting trapped with having to use core0 and core1 with certain constraints (timers, DMA, interrupts, etc) that then interfere with other portions of the chip or even might be mutually exclusive.
* [devkit] usb-c interface?
* [devkit] more boards with PICO form-factor that will fit better on standard breadboards. The devkit is sooo wide! (I totally understand though because the WROOM/WROVER modules are rather "fat" themselves.)

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Re: What would you like to see in The Next Chip?

Postby pataga » Sat Jun 06, 2020 11:13 am

Big thumbs up for :
1. RISC V cores - simply because you will have more software engineers willing to invest the effort if the knowledge is transferable, and so, a bigger pool of software engineers who can contribute to developing drivers, toolchain improvements, applications.
2. DMA to/from PSRAM to SPI, I2S, DAC - to support graphic LCDs, audio applications, with working (no byte-ordering workarounds) 8/16/24 bit support.

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Re: What would you like to see in The Next Chip?

Postby fearless_fool » Sat Jul 11, 2020 10:56 pm

The more things that can wake the processor from sleep, the better.

One that I've not seen anywhere is a "sleepy UART" mode that draws almost no current until a start bit is seen, then proceeds to capture the entire first byte as it wakes the processor.

If you want a longer discussion about optimizing the RF MAC layer for low power, we should start a separate thread. (I was chair of the IEEE 802.15.4B standards body and co-founder of Ember Corporation, so I've done a lot of work here.) Exploiting RF capture effects, "fast-fail" on corrupted packets, synchronizing transmitter and receiver to minimize the time the receiver is powered on and a few other techniques come to mind. Some of that can be done within the 802.11 standard, some require bending the rules...

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