ESP32 Forum

Is it possible to use esp32 without rtos, and how to make it?

Possible-ish to use app CPU as realtime coprocessor. https://github.com/espressif/esp-idf/bl ... Kconfig#L4

But don't think there is a framework or example for doing it yet. And all the networking stuff would still run under rtos on the pro CPU and you'd have to do some inter process[or] communication.

What is the use case? Arduino experience is kind of like fake non-rtos.

As WiFive said, it's absolutely possible, with different levels of stand-alone-ness. What specific thing are you trying to archieve? If we know that, we'll be able to help you more.

Hi! You asked about use case. Here's it.
I'm very interested in this topic because I develop some specific AI/AGI algorithms. From what looks prospective at the moment, an ESP32-S2 chip could work as a "cell" in super matrix computing. A PCB board could hold, say, 100 such chips. They're funny cheap and power efficient. A board could top at 20 W. While first row of super matrix is listening big set of sensors, next rows will get information from previous rows and as long as row depth goes on, the less volume of computing work is expected. Comparing to graphics cards (CUDA, etc.), less power source is anticipated. I just need to evaluate total performance to get right estimates for the price-performance ratio ans so a future of the idea.
The "cell" itself is supposed to compute single math matrix operation, so code is tiny but the matrix is bulky. I really don't need Wi-Fi, BT and many other interfaces but low level SPI only, for inter-chip communication. Power saving modes are critically important because I hope full board will consume 5 W in awerage, 20 W is a peak.
That's it. As you can see, FreeRTOS is mostly unneeded part just eating RAM, so I'd like to get rid of it on first favorable occassion. And ESP32-S2 chip appears preferred versus base ESP32 and its replacement ESP32-S3. Because there's no work for second core.
I will appreciate any comments, concerns and ideas.
Thank you for reading a long story

From your description i think that better choice may be esp32 C3, with RISC V main CPU. Also 1 core only and power consumption more efficient. I dont have experience, but i think that it may be much easier to use RISC V standard for what you need (freertos-less OS).

nvtby_espf wrote: ↑

Sun Apr 04, 2021 5:11 pm

Comparing to graphics cards (CUDA, etc.), less power source is anticipated. I just need to evaluate total performance to get right estimates for the price-performance ratio ans so a future of the idea.

That is a bit of a weird use case: you haven't even got an idea of how much memory you need, but you already decided the amount of memory FreeRTOS takes up (whatever that amount is) is too much.

Also, I really, really think you're underestimating the brute power of graphics cards. Let's do a quick back-of-the-envelope calculation to get some idea of what the difference is. An ESP32 is not really optimized for floating point operations, if you really squeeze it you *might* get 1 FLOP/cycle out of it, and that is more or less a theoretical upper bound, I'm decently sure our FPU isn't event that fast. That's 240M flops/sec per ESP32. Let's say when computing at full speed, they use about 50mA. That's 0.165 watt. So for a 20 watt power budget, you get 121 ESP32s. You'll also get some losses because you need to power flash, buck converters etc, so let's round it to a nice 100 ESP32 chips. That's a total of 24GFLOPS of computing power, right there.

Now compare that to e.g. a NVidia Jetson TX2. This little board still is within your power budget, using 15W max. However, in computing power, it hands you 1.33 teraflops of computing power. That is a whopping 55X more computing power, for less power usage and likely a smaller form factor.

Look, I like the ESP32 as much as the next guy, and things like the ESP32S3 (which has some AI optimizations) may tilt the balance a bit, but for now an array of tiny general-purpose microcontrollers to replace silicon that is 100% dedicated to computing just does not make sense.

Thank you for detailed reply! In general, I mostly share same thoughts. But all nuances matter. Nvidia makes great devices. The problem appears with their software. I really don't neeed tensor math over Python, proposed by mainstream manufactures. I use another math and so need just "bare metal" coding. CUDA allows such choice. ESP32 too. ESP with 2 MB RAM holds a matrix of size I need. AI math doesn't need accuracy of 64 bits. In theory, even 8 bits are good. That's enough for single cell. The only thing I need for now, is how test prototype will perform. For ML/AI, only trainig phase is CPU hungry, inference has pretty moderate demands. I won't train model on the ESP. I will train it on CUDA or multi-core Intels.