Power Management settings cause spi delays

newsettler_AI
Posts: 114
Joined: Wed Apr 05, 2017 12:49 pm

Power Management settings cause spi delays

Postby newsettler_AI » Thu Jan 31, 2019 7:21 pm

Hi,

I' using ESP32 as spi master for driving LCD over spi, clock freq configured as 60MHz.
Graphic library uses custom tick handler esp_register_freertos_tick_hook().
I'm loading picture from spiffs image and draw it on LCD.

After I enabled Component config -> Power Management -> Support for power management I'm facing huge delays in picture drawing. All other settings remains same.

On logic analyzer I noted taht there are delays between commands:

POWER SAVE DISABLED:
delay between commands ~56ms
spi_powersave_off.jpg
spi_powersave_off.jpg (127.36 KiB) Viewed 1517 times


POWER SAVE ENABLED:
delay between commands ~350 ms
spi_powersave.jpg
spi_powersave.jpg (118.84 KiB) Viewed 1517 times


As I see, there is special handle in spi driver for this configuration (CONFIG_PM_ENABLE):
https://github.com/espressif/esp-idf/bl ... ter.c#L190

What should I take into account if enable Power save? Why delays apear? Maybe it affects on ticks handling somehow?

Reagrds

newsettler_AI
Posts: 114
Joined: Wed Apr 05, 2017 12:49 pm

Re: Power Management settings cause spi delays

Postby newsettler_AI » Sat Feb 02, 2019 3:35 pm

Any ideas where I should to dig?

ESP_igrr
Posts: 1656
Joined: Tue Dec 01, 2015 8:37 am

Re: Power Management settings cause spi delays

Postby ESP_igrr » Sun Feb 03, 2019 12:38 am

Do you only enable CONFIG_PM_ENABLE or also some other PM related options (such as, initialize PM at startup)? Do you call esp_pm_configure to set parameters such as minimum and maximum frequency? Do you enable "FreeRTOS Tickless Idle" option?
Depending on answers to those questions it might be either that this is because of the tick interrupt being skipped (due to tickless idle) or because of some other reason.

newsettler_AI
Posts: 114
Joined: Wed Apr 05, 2017 12:49 pm

Re: Power Management settings cause spi delays

Postby newsettler_AI » Mon Feb 04, 2019 1:27 pm

Change made in sdkconfig are below. Application code remais unchanged.

Power management:
pm_conf.jpg
pm_conf.jpg (53.44 KiB) Viewed 1388 times
FreeRTOS:
freertos_conf.jpg
freertos_conf.jpg (63.74 KiB) Viewed 1388 times
Paremeter Minimum number of ticks to enter sleep mode was set to 3 by default

ESP_igrr
Posts: 1656
Joined: Tue Dec 01, 2015 8:37 am

Re: Power Management settings cause spi delays

Postby ESP_igrr » Tue Feb 05, 2019 12:48 pm

If tickless idle is enabled, FreeRTOS will skip ticks when these ticks do not cause tasks to unblock or timeouts to expire. The library you are using was probably written with the assumption that FreeRTOS ticks always happen at the same interval. The assumption becomes invalid if tickless idle is used. You might be able to modify the library to use a different method of getting periodic interrupts, such as Timer Group hardware timers or esp_timer library.

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