Document Requests

michprev
Posts: 87
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sat Nov 17, 2018 5:41 pm

AFAIK there is also bug in WP settings (https://github.com/espressif/esp-idf/bl ... ruct.h#L56) both with user commands and SPI flash commands.

michprev
Posts: 87
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sun Nov 18, 2018 10:02 am

michprev wrote:
Sat Oct 20, 2018 11:33 am
  • [SPI] CS setup time does not work in full duplex
I don't think you realise how huge problem this is. Full-duplex is the most common setup and most SPI peripherals require CS active several clocks before the data transfer.

michprev
Posts: 87
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sun Nov 18, 2018 9:22 pm

https://github.com/espressif/esp-idf/bl ... #L382-L438 this is not documented

And what does this mean? https://github.com/espressif/esp-idf/bl ... #L843-L846
Is it the same issue as the one above?

michprev
Posts: 87
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sat Nov 24, 2018 3:58 pm

Setting SPI_CLKCNT_H too high in SPI_CLOCK_REG register makes in some cases (probably depending on SPI_CLKCNT_N) stop SPI working. This is not documented.

michprev
Posts: 87
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sun Nov 25, 2018 8:43 am

https://docs.espressif.com/projects/esp ... own-issues
Half duplex mode is not compatible with DMA when both writing and reading phases exist.
What does it mean exactly? When SPI_DOUTDIN in SPI_USER_REG is set to zero this issue occurs?

ESP_Lvxinyue
Posts: 28
Joined: Fri Dec 25, 2015 6:13 am

Re: Document Requests

Postby ESP_Lvxinyue » Tue Nov 27, 2018 6:24 am

michprev wrote:
Sun Nov 18, 2018 10:02 am
michprev wrote:
Sat Oct 20, 2018 11:33 am
  • [SPI] CS setup time does not work in full duplex
I don't think you realise how huge problem this is. Full-duplex is the most common setup and most SPI peripherals require CS active several clocks before the data transfer.
In full-duplex mode, setting SPI_CS_SETUP results in 1.5 SPI clock cycles between CS active and data transfer, while clearing this bit results in half an SPI clock cycle in between.

ESP_Lvxinyue
Posts: 28
Joined: Fri Dec 25, 2015 6:13 am

Re: Document Requests

Postby ESP_Lvxinyue » Tue Nov 27, 2018 6:26 am

michprev wrote:
Sat Nov 24, 2018 3:58 pm
Setting SPI_CLKCNT_H too high in SPI_CLOCK_REG register makes in some cases (probably depending on SPI_CLKCNT_N) stop SPI working. This is not documented.
PI_CLKCNT_H=⌊SPI_CLKCNT_N+1/2 – 1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L

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