I2C Pull-up resistance design to prevent NACK's

ptipaldo
Posts: 4
Joined: Sun Mar 23, 2025 8:05 pm

I2C Pull-up resistance design to prevent NACK's

Postby ptipaldo » Sun Mar 23, 2025 9:02 pm

Hi all,
I just started working with a ESP32-C3-MINI-1-H4 chip as part of a custom board that was designed. The primary point of focus is the I2C connection/communication with an IMU sensor. I set up a basic I2C communication program, even to use the i2c_master_probe() function as part of the "driver/i2c_master.h" header. However, I get an error with this, an any attempt to read the IMU with i2c_master_receive() failed with a ESP_ERR_TIMEOUT, which based on the ESP32 I2C documentation here, "If you get ESP_ERR_TIMEOUT while xfer_timeout_ms was parsed correctly, you should check the pull-up resistors." https://docs.espressif.com/projects/esp ... 2c%20start
After enabling the internal pullups in the i2c_master_bus_config with .flags.enable_internal_pullup = true, I know get ESP_ERR_NOT_FOUND, and an error for I2C hardware NACK detected. My current implementation is using 10K pull-up resistors on both SDA and SCL. I am wondering the pull-up resistors are too high of an impendence and is causing the NACK's, since enabling the internal pull-up resistors would drop the equivalent resistance to 8.18kOhms.
My math says based on the typical current sink of 28mA in the esp32 chip via the datasheet and the Vlow of .3*Vdd and Vhigh of .7*Vdd from the esp32 I2c design documentation and my input voltage of 3.3V, that the pull-up resistors should be 86 Ohms, which seems very low. In fact, the I2C documentation specifies that the pull-up resistors should be between 1k and 10k.
Anyone have any ideas?

Sprite
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Re: I2C Pull-up resistance design to prevent NACK's

Postby Sprite » Mon Mar 24, 2025 12:26 am

Yeah, 10K and 8.8K feel like too high. From what I can see in the specs, at 3.3V the minimum pullup resistance is 1K. They don't give a max pullup resistance (it depends on your circuits parasitic capacitance) but in my experience something like 3K3 works fine.

You may also want to stick a scope on the I2C lines to be sure. If the signal looks OK (rise times are fine) then the pullup is not your issue.

ptipaldo
Posts: 4
Joined: Sun Mar 23, 2025 8:05 pm

Re: I2C Pull-up resistance design to prevent NACK's

Postby ptipaldo » Mon Mar 24, 2025 10:00 pm

Thanks so much! This is what I assumed. I can't scope out my current implementation since to don't have access a scope, and the ESP chip I am using is a SMD that has it's pins fully enclosed anyways. Hence why I was relying on the math to prove that it was not working due to the pull-up resistance. I'm going to try and remove those pull-up resistors and put on some 3k3 ones and see if that works.

eriksl
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Joined: Thu Dec 14, 2023 3:23 pm
Location: Netherlands

Re: I2C Pull-up resistance design to prevent NACK's

Postby eriksl » Sun Apr 20, 2025 1:45 pm

Usually the minimum is something like 2.2 k, 4.7 k is a safe default.

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