Logic analyzer on ESP32 for self-diagnostics

[ok-home]

Added support for ESP32P4

Not sure if you're interested, but if you squirrel around in the SDK a bit, you can potentially make the P4 go much faster, probably up to 200MHz or so. Very high-level view: At least the PARLIO peripheral can also accept an external clock signal; I think this is specced for up to 80MHz but it can actually go a lot faster. (Possibly the LCDCAM module can do this as well, I haven't checked.) Additionally, if you make the PSRAM use the system PLL rather than the MPLL, you free that up for use as a random clock generator. You can then abuse the 50MHz output pin intended for Ethernet PHYs to output the clock signal; connect the PARLIO/LCDCAMs clock input pin to the same pin and it'll run on that clock signal. (But do note that on some silicon revs of the P4, the MPLLs clock frequency isn't quite stable: you may want to look into using other PLLs for that.)

Thanks for the advice.
I will definitely make a version for parlio
But I looked at the clock sources for PARLIO and CAM
For LCD/CAM, clocking is only from XCLK, PLL160 and APL
For PARLIO, an external clock is added. As far as I understand hardware (and I don't understand it very well), for stable data reception, you need to have at least *2 reference frequency, so jumping out of the standard 160/2 MHz will not work without changing the reference frequencies.
Since this project is intentionally done in such a way as to have minimal impact on running applications, changing the base frequencies is wrong

[ok-home]

Added support for ESP32P4 PARL_IO module
- Only CLI interface is supported
- Data reading in parallel mode 8/16 bit.
- For LCD_CAM module, one GPIO is required for PCLK signal
- PARL_IO module supports 8/15 bit. Bit 15 is used for trigger (HW limitation)
- IRQ/ETM trigger mode can be selected, ETM mode requires one additional free GPIO
- Maximum sampling rate does not depend on the number of channels and the type of memory for the buffer (Ram/Psram) and is 80 MHz (for PSRAM frequency = 200 MHz)
- The number of samples is limited only by the size of free memory (Ram/Psram), The maximum number of samples can be 32,000,000 for modules with 32 Mbyte Psram.

[jgustavoam]

Very interesting project.
I have been studying this type of project for many years.
I've evaluated some ESP32 Logic Analyzer projects, but none of them sparked much interest due to their limitations.
I will study and test your project. Thanks for sharing.

Some projects already studied by me (I need to review them):

https://github.com/EUA/ESP32_LogicAnalyzer
https://github.com/Ebiroll/esp32_sigrok
https://github.com/pschatzmann/logic-analyzer


This guy has some really good projects. I haven't tested it yet
https://iosoft.blog/2022/04/11/edla/

[ok-home]

Thank you for your interest in the project.
I carefully studied all the projects linked to by you, and some of the information in my project regarding the SUMP protocol was taken from them.
Unfortunately, the SUMP protocol implementation in sigrok has some bugs that I couldn't overcome, so communication with sigrok is currently primarily via the cli interface and regular .bin files. This is a more flexible approach to configuring sample capture parameters. A simple web interface was written solely for visualization.
Another key difference from these implementations (and this is what the project was created for) is the use of ESP32 capabilities to switch any GPIO to the analyzer input without the use of external wires, directly within the project, on a working prototype. It's enough to simply connect this project as a component (you can even view pins that aren't routed to external pins in some modules).
Using DMA for sample capture allowed us to achieve the highest possible speeds with minimal impact on the project under study.