Is PLL 480 MHz or 320 MHz fixed per chip?

[LOLKP928]

I'm doing some bare metal dev work on the ESP32 and noticed something when playing around with the CPU frequency.

APB is supposed to be 80 MHz when the CPU clock source is PLL. Assuming APB_CLK is obtained from the PLL_CLK, the divider must be 4 if the PLL is 320 MHz and 6 if the PLL is 480 MHz. How ever, when i switch the PLL to 480 MHz (needed to run the CPU at 240 MHz), the APB_CLK drops to 53 MHz. This can be explained by the PLL clock staying at 320 MHz but the divider becoming 6.

So is the PLL clock speed fixed per chip? i.e it runs either at 480 or 320? Did I do the switching incorrectly? I set RTC_CNTL_SOC_CLK_SEL and CPU_CPUPERIOD_SEL as per the TRM, was there something else I should've set?

[lichurbagan]

Your APB drop happens because the 480 MHz PLL never activates. The ESP32 has two PLL modes, and you must explicitly switch to the 480 MHz one. If you only change the CPU dividers, the chip stays on the 320 MHz PLL.

You must enable the 480 MHz PLL before changing the CPU source. The ESP-IDF clock code shows the correct sequence and required waits. Missing this step leaves APB stuck at 320 MHz ÷ 6.

Check Espressif’s TRM clock chapter and the ESP-IDF rtc_clk.c code. These show the PLL select bits and full switch routine:
https://gitlab.informatik.uni-bremen.de ... /rtc_clk.c

https://documentation.espressif.com/esp ... al_en.html

[LOLKP928]

Your APB drop happens because the 480 MHz PLL never activates. The ESP32 has two PLL modes, and you must explicitly switch to the 480 MHz one. If you only change the CPU dividers, the chip stays on the 320 MHz PLL.

You must enable the 480 MHz PLL before changing the CPU source. The ESP-IDF clock code shows the correct sequence and required waits. Missing this step leaves APB stuck at 320 MHz ÷ 6.

Check Espressif’s TRM clock chapter and the ESP-IDF rtc_clk.c code. These show the PLL select bits and full switch routine:
https://gitlab.informatik.uni-bremen.de ... /rtc_clk.c

https://documentation.espressif.com/esp ... al_en.html

i get that, but how is the 480 PLL not activating? As per 7.2-2. on page 167 of the TRM, the registers I set are allthat's mentioned. There's no mention of any other registers needing to be set to switch to 480 MHz.

[MicroController]

As per 7.2-2. on page 167 of the TRM, the registers I set are allthat's mentioned. There's no mention of any other registers needing to be set...

Unfortunately, information in the TRMs is often incomplete, and almost always so in regard to things you're supposed to only use via the IDF. Consequently, the TRM not mentioning some register, bit, or required procedure does not imply there is none to be considered.

The definitive and most complete source of information in these cases is the respective IDF source code.