ESP32-S31 :)

[MicroController]

Oh boy, looks like there's a new toy coming up
So much fun stuff to play around with! Can't wait

[Demirug]

I have spotted it, too. Based on what is in the IDF it looks kind of a mix of the P4 and S3 with some more extras.

[lichurbagan]

When will it come?

[MicroController]

Based on what is in the IDF it looks kind of a mix of the P4 and S3 with some more extras.

Right? JPEG, 2D DMA, PPA, Bitscrambler, ParlIo, ECC,... Let's see what the HP vs. LP core can do.

[Demirug]

Based on what else is in this folder I would say the HP parts is a 400MHz dual core Risc V. So more or less what we kow from the P4 I would assume. Which make sense as it was stated before that the Xtensa core will be faced out for new chips.

It also looks like there is more GPIOs. Full range from 0 to 62.

[rudi ;-)]

... dual core Risc V ...

... more GPIOs ...to 62

... one more ("SOC_GPIO_PIN_COUNT" ) ...up to 63
... but max in / out 62 ( 63 )

... higher boot regions
... extended IRAM segments
... optimized boot processes and shared RAM regions .. released after RTOS startup i 'guess'
... optimized drivers for timer, UART, etc.
... few more things can be read in the IDF

oh yes, this is an untamed RISC V beast and has extreme #penguin potential 'loveIT'

hi folks

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#define SOC_CPU_CORES_NUM               (2U)
#define SOC_INT_CLIC_SUPPORTED          1        // RISC-V CLIC interrupt controller
#define SOC_LP_CORE_SUPPORTED           1        // Dedicated Low-Power core
#define SOC_HP_CPU_HAS_MULTIPLE_CORES   1
#define SOC_CPU_HAS_FPU                 1        // Hardware Floating Point Unit
#define SOC_CPU_HAS_PIE                 1        // Position-Independent Executable coprocessor

high-performance RISC-V core (HP domain) + ultra-low-power RISC-V core (LP domain)
Full ( RV32IMAFCP ) baseline + modern extensions (CLIC, PMP, FPU, PIE, branch predictor, hardware loops)

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#define SOC_GPIO_PIN_COUNT                 63
#define SOC_GPIO_IN_RANGE_MAX           62
#define SOC_GPIO_OUT_RANGE_MAX          62
#define SOC_GPIO_VALID_GPIO_MASK        (0x7FFFFFFFFFFFFFFF)   // 63 bits set

Highest GPIO count of any Espressif chip ever released (S3 = 45, P4 = 56, S31 wins with 63)

4× high-performance UARTs
System timer (2 counters, 3 alarms)
eFuse with key-purpose field
Flash encryption (XTS-AES-128/256)
Full LP-IO subsystem (independent clock, independent wakeup)
Deep-sleep wakeup on GPIO0–7
40 MHz XTAL support
Shared I/D cache with write-back and freeze
Physical Memory Protection (PMP) with 128-byte granularity

Native RISC-V RV32IMAFCP + CLIC + PMP

The ESP32-S31 is a real, high-end RISC-V monster with 63(62) GPIOs and a modern heterogeneous dual-core design. It is currently in the early bring-up phase in ESP-IDF master (Dec 2025), but the hardware capabilities are already fully defined and vastly superior to the ESP32-S3. Massive thanks to the espressifer who pulled the real soc_caps.h — this is the smoking gun the community has been waiting for!

woke up

[MicroController]

Argh. Got too excited by the "S3" in the name.
Can't find

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#define SOC_WIFI_SUPPORTED

or

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#define SOC_BT_SUPPORTED

So maybe more of a down-spec'd P4 than an upgraded S3?

[Sprite]

I'm obviously not gonna disclose anything about future products, but some food for thought: if a new product would not have radios, wouldn't it make more sense to call it the ESP32-P41?

[Demirug]

Well, at least the Interrupt list contains quite some interrupts for a a modem with wifi, bt and ble.

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    volatile interrupt_core0_modem_wifi_mac_intr_map_reg_t modem_wifi_mac_intr_map;
    volatile interrupt_core0_modem_wifi_mac_nmi_intr_map_reg_t modem_wifi_mac_nmi_intr_map;
    volatile interrupt_core0_modem_wifi_pwr_intr_map_reg_t modem_wifi_pwr_intr_map;
    volatile interrupt_core0_modem_wifi_bb_intr_map_reg_t modem_wifi_bb_intr_map;
    volatile interrupt_core0_modem_bt_mac_intr_map_reg_t modem_bt_mac_intr_map;
    volatile interrupt_core0_modem_bt_bb_intr_map_reg_t modem_bt_bb_intr_map;
    volatile interrupt_core0_modem_bt_bb_nmi_intr_map_reg_t modem_bt_bb_nmi_intr_map;
    volatile interrupt_core0_modem_lp_timer_intr_map_reg_t modem_lp_timer_intr_map;
    volatile interrupt_core0_modem_coex_intr_map_reg_t modem_coex_intr_map;
    volatile interrupt_core0_modem_ble_timer_intr_map_reg_t modem_ble_timer_intr_map;
    volatile interrupt_core0_modem_ble_sec_intr_map_reg_t modem_ble_sec_intr_map;
    volatile interrupt_core0_modem_i2c_mst_intr_map_reg_t modem_i2c_mst_intr_map;
    volatile interrupt_core0_modem_zb_mac_intr_map_reg_t modem_zb_mac_intr_map;
    volatile interrupt_core0_modem_bt_mac_int1_intr_map_reg_t modem_bt_mac_int1_intr_map;

So I still think it's taking the best parts from the S3 and P4 with some extras

[rudi ;-)]

Well, at least the Interrupt list contains quite some interrupts for a a modem with wifi, bt and ble.

... so many usefull INT

Can't find

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#define SOC_WIFI_SUPPORTED

or

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#define SOC_BT_SUPPORTED

So maybe more of a down-spec'd P4 than an upgraded S3?

So many usefull modems

Code: Select all

....
    [ETS_MODEM_WIFI_MAC_INTR_SOURCE] = "MODEM_WIFI_MAC",
    [ETS_MODEM_WIFI_MAC_NMI_INTR_SOURCE] = "MODEM_WIFI_MAC_NMI",
    [ETS_MODEM_WIFI_PWR_INTR_SOURCE] = "MODEM_WIFI_PWR",
    [ETS_MODEM_WIFI_BB_INTR_SOURCE] = "MODEM_WIFI_BB",
    [ETS_MODEM_BT_MAC_INTR_SOURCE] = "MODEM_BT_MAC",
    [ETS_MODEM_BT_BB_INTR_SOURCE] = "MODEM_BT_BB",
    [ETS_MODEM_BT_BB_NMI_INTR_SOURCE] = "MODEM_BT_BB_NMI",
    [ETS_MODEM_LP_TIMER_INTR_SOURCE] = "MODEM_LP_TIMER",
    [ETS_MODEM_COEX_INTR_SOURCE] = "MODEM_COEX",
    [ETS_MODEM_BLE_TIMER_INTR_SOURCE] = "MODEM_BLE_TIMER",
    [ETS_MODEM_BLE_SEC_INTR_SOURCE] = "MODEM_BLE_SEC",
    [ETS_MODEM_I2C_MST_INTR_SOURCE] = "MODEM_I2C_MST",
    [ETS_MODEM_ZB_MAC_INTR_SOURCE] = "MODEM_ZB_MAC",
    [ETS_MODEM_BT_MAC_INT1_INTR_SOURCE] = "MODEM_BT_MAC_INT1",
....

WoWZa