Availability of Xtensa core extensions in ESP32-S3

[alex000090]

Dear all,

I have some misunderstanding about Xtensa core used in ESP32-S3.
According to Xtensa Instruction Set Architecture the boolean registers, boolean operations and some "TIE" extensions (like FLIX and SIMD) can be presented in some Xtensa LX chips. But as far as I understood, it is options.
May someone help me to understand, are these features presented in the Xtensa CPU into ESP32-S3 and how it can be used?

Briefly, I tried to simply use the line below to test compiler ability, but I caught "bad register name: b0" error which tells one nothing about hardware.

Code: Select all

asm volatile ("wsr b0, 1");

[MicroController]

See https://github.com/espressif/esp-idf/bl ... core-isa.h
The boolean registers are there (used by the FPU) (plus some other pretty cool stuff), no FLIX, but Espressif's own "Processor Instruction Extensions" ("PIE") SIMD are available, documented (only) in the ESP32-S3 TRM.
The boolean registers are used by the compiler automatically, e.g. for float (FPU) comparisons. The PIE/SIMD instructions aren't supported by the compiler, but they are by the assembler; so to make use of them you can employ either inline assembly or stand-alone assembly (.S) files/functions.

(Btw, I think you cannot explicitly write to a single boolean register. They all live inside the "Special Register BR", so "MOVI %[tmp], 0; WSR.BR %[tmp]" for example should clear them all.)

[alex000090]

Thanks for the answer! Now it's clearer to me. And another question: I don't quite understand how many registers are in the ESP32-S3. For example, the TDS specifies the number of QRs for 8, but does that mean 8 per core or 8 per chip?

[MicroController]

Each core has its own full set of CPU registers. This includes the core architecture's "address registers" as well as the FPU and PIE registers.

[knutbrut]

Sorry to restart an old thread. Does this mean that:

1. For the xtensa lx7 instruction set the boolean instructions like OLT.S, BT, BF, etc. are unavailable for the ESP32-S3. If so can you provide example code for the feature set that replaces this functionality?

2. You state that each core has it's own full set of CPU registers. Does this mean that each CPU has it's own dedicated FPU? I can't find this clearly stated in the documentation.

Thank you

[MicroController]

Does this mean that:
... the boolean instructions like OLT.S, BT, BF, etc. are unavailable for the ESP32-S3.

No.

Does this mean that each CPU has it's own dedicated FPU?

I assume it does. Haven't actually benchmarked it, but I have also never seen anything mentioned anywhere about some synchronization/arbitration mechanics w.r.t. access to "the" FPU.

[knutbrut]

If so I would suggest correcting the Table 1.5-1 of the ESP32-s3 TRM. The BR registers are not listed here which is confusing.

[MicroController]

all kinds of registers related to ESP32-S3’s extended instruction set

The S3's PIE/ISA extensions don't use the BRs, so...
For the full list of (non-PIE) registers, you may refer to Cadence's ISA summary.

(Not hooking up the BRs to the PIE vector comparison instructions may actually have been an unfortunate oversight by Espressif.)