How to solve the problem of ICACHE being disabled in EFUSE of ESP32-C3?

[Eltrion]

I accidentally enabled EFUSE_DIS_ICACHE in the efuse of ESP32-C3, and now the program keeps rebooting. Is there any solution? Also, does the USB Serial module of ESP32-C3 have an efuse bit to disable the function where operating the RTS pin causes the ESP32-C3 to reset?

Code: Select all

ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x1 (POWERON),boot:0xc (SPI_FAST_FLASH_BOOT)
ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x7 (TG0WDT_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
Saved PC:0x40050f50
--- 0x40050f50: Cache_Travel_Tag_Memory in ROM
ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x7 (TG0WDT_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
Saved PC:0x40050f4e
--- 0x40050f4e: Cache_Travel_Tag_Memory in ROM
ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x10 (RTCWDT_RTC_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
ESP-ROM:esp32c3-api1-20210207
Build:Feb  7 2021
rst:0x7 (TG0WDT_SYS_RST),boot:0xc (SPI_FAST_FLASH_BOOT)
Saved PC:0x40050f52

[Sprite]

Nope, I think that was mostly a chicken bit and there isn't any software support for chips with that fuse being blown. Time to rework the board and put a new ESP32-C3 on it I'm afraid. On the C3 I don't think there's a way to disable the RTS/DTR reset; on later chips firmware can toggle a bit to disable it.

[Eltrion]

Which models are referred to by subsequent chips? I know that ESP32-S2 and ESP32-S3 support standard USB functionality, but their packages are too large. I want a chip with a small package that supports USB Serial virtual COM port.

[Sprite]

I'm gonna say from the C6 on (so the C5, C6, C61, H2, P4, but be sure check the TRM to see if the register bits are there). Bit is the USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS bit (make sure to set the update bit as well).