What is the right way to adjust the sampling time of the ADC on the ESP32-S3?

[gaby1010]

Before a conversion can begin, the SAR ADC must connect the input source to the internal sample-and-hold capacitor for long enough to allow it to charge to the input voltage. I am trying to understand how this process is modelled on the ESP32-S3 (ESP-IDF v6.0.1). In adc_ll.h there is the function adc_ll_set_sample_cycle() with the comment:

Set adc sample cycle for digital controller.
@note Normally, please use default value.
@param sample_cycle Cycles between DIG ADC controller start ADC sensor
and beginning to receive data from sensor.
Range: 2 ~ 0xFF.

My question:
Does adc_ll_set_sample_cycle() directly control the sampling time of the SAR ADC’s internal sample-and-hold circuit (i.e. how long the input is connected to the sampling capacitor), or does it configure something else? How can the actual sampling time be calculated in nanoseconds? Any clarification from Espressif or anyone who has characterised this would be much appreciated.

[vvb333007]

I am not 100% sure but I would check if this cycles are APB cycles (80MHz).