Where is the Technical Reference Sheet

[hehongbo]

I just wanna run u-boot on it, but I can only find out the address of peripherals by esp-idf sdk
Could you please provide the Technical Reference Sheet ?

[Sprite]

The technical reference manual is not finished yet, sorry.

[hehongbo]

The technical reference manual is not finished yet, sorry.

OK
There is another point: I find your current approach quite unusual. You are enabling the mwdt, rwdt, and swd simultaneously within the BootROM; in reality, this should be handled in the bootloader, and hardcoding it into the BootROM may not be a sound strategy.

[Sprite]

There is another point: I find your current approach quite unusual. You are enabling the mwdt, rwdt, and swd simultaneously within the BootROM; in reality, this should be handled in the bootloader, and hardcoding it into the BootROM may not be a sound strategy.

I'd love to hear your reasons for stating that's not a sound strategy.

For the reasons to enable them early: First of all, from what I recall the bootrom does not even touch the WDTs as they start out enabled in hardware. The thing is that we want 100% certainty that some glitch doesn't stop the boot process cold without having some way of recovering. If we only enable the WDTs in the bootloader, there's a chance that somehow the CPU ends up in an infinite ROM either in the bootrom or in the bootloader before it had a chance to enable the WDTs, meaning the chip is dead in the water until something manually resets it. That's undesirable.

[bastel]

Is it already known, when the Technical Reference will be availible?

[rudi ;-)]

I think the early watchdog activation strategy makes sense from a system reliability perspective. While moving watchdog configuration into the bootloader provides more software flexibility, enabling the basic protection already at hardware/BootROM level avoids a critical window where the device could become permanently stuck before the bootloader gains control. For a modern SoC like the ESP32-S31, early recovery capability seems like a reasonable design choice.


4.1.4.9 Watchdog Timers (WDT)
ESP32-S31 contains three digital watchdog timers: one in each of the two timer groups (called Main System
Watchdog Timers, or MWDT) and one in the LP system (called the RTC Watchdog Timer, or RWDT).
In SPI Boot mode, RWDT and the MWDT in timer group 0 are enabled automatically in order to detect errors that
may occur during the flash boot process and facilitate recovery.
ESP32-S31 also has one analog watchdog timer: Super watchdog (SWD). It is an ultra-low-power circuit in
analog domain that helps to prevent the system from operating in a sub-optimal state and resets the system if
required.
Feature List
• Four stages, each with a separately programmable timeout value and timeout action
• Timeout actions:
– MWDT: interrupt, HP CPU reset, HP core reset
– RWDT: interrupt, HP CPU reset, HP core reset, system reset
• Flash boot protection under SPI Boot mode at stage 0:
– MWDT0: HP core reset upon timeout
– RWDT: system reset upon timeout
• Write protection that makes WDT register read only unless unlocked
• 32-bit timeout counter
• Clock source:
– MWDT: PLL_F80M_CLK, RC_FAST_CLK or XTAL_CLK
– RWDT: LP_DYN_SLOW_CLK

[drmikej]

Is it already known, when the Technical Reference will be availible?

Any answer to this question - even an early draft would be helpful in using the S31