ESP32-S31 :)

[andylinpersonal]

Seems like it contains no H264 codec and MIPI DPHY, the general-purpose OTG FS port has also been removed.

1. LP GPIO is reduced from 16 to 8. c.f. S3 has 22.
2. PSRAM is still at dedicated MSPI pins like P4, but reduced from HSPI (16 lines) to OSPI (8 lines).
3. Flash pins are multiplexed with normal GPIOs again so the free GPIO may need to reduce by 7 and yield the same available GPIO pins as P4. (QSPI requires 6 pins and VDD_SPI is usually used to power the flash, and those are dedicated pins on P4)
4. The 2-channel DAC gone from s3 has been revived and upgraded to 12bit (?) .
2 DAC units, 1 2-channel 10bit DAC, and another 2-channel 12bit DAC.
5. CORDIC accelerator for advanced control, can also be found in some high-end STM32 and industrial MCUs.
6. One unit of 2-in, 2-out LP DMA in LP domain (?) can make LP app more capable.
7. HP cores have sv32 virtual memory system, capable of running (full) Linux [!!!]

Datasheet has been published

[MicroController]

BTW, how to add link in post without showing the full bloating part?

Code: Select all

Click [url=http://example.com]here[/url]

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Code: Select all

[url=https://github.com/espressif/esp-idf/blob/35e0c8a343e2e5e7d521b99da53634eeb01e52cf/components/soc/esp32s31/include/soc/soc_caps.h#L181]LP GPIO[/url] is reduced from 16 to 8.

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"LP GPIO is reduced from 16 to 8."

[andylinpersonal]

Thanks bro.

[eriksl]

I think I already mentioned this, but I'm not that impressed. I see a S3 with RISC V cores, which, in itself, for developers isn't really that important. Most "improvements" are in the area of IP protection, which isn't really my cup of tea.

I'd rather see some, seemingly artificial, limitations lifted. Like for example the 14 bit wide LEDPWM counters. A bit more internal RAM, as whatever amount of PSRAM is added, internal DRAM fills up with data from IDF code that we can't control. All my data, including stacks of threads, is already in PSRAM but still DRAM is filling up.

Also an idea for a nice improvement: run the SPI from a faster clock or introduce a fractional divider. I don't need higher SPI speeds, but only having 80, 40, 23 ... MHz available is a pain.