esp32-c6 riscv : Interrupt 1 does not trigger.

[watchdog40]

Hello.
I am programming directly in RISC-V on an ESP32-C6.
I want to test triggering an interrupt from the system timer.
The system timer part works fine, but interrupt 1 isn't triggering!!
However, I have successfully run a timer test managed by interrupt 7 of the Core Local Interrupt (CLINT).

I must be overlooking something—but what?
Here is my RISC-V code:

Code: Select all

/************************************/
/*       Timer systeme   chap 13      */
/***********************************/
/* no  paramètre */
testAlarmeTimerSysteme2:                 # INFO: testAlarmeTimerSysteme2
    addi    sp, sp, -8           # save registres
    sw      ra, 0(sp)
  
    csrrw   zero, mie, x0        # raz interruptions
    li t0,0b1100010001000
    csrrw   zero, mstatus, t0    # Write 1 to enable the global machine mode interrupt. (R/W)
    
    li s0,SYSTIMER
    lw t0,SYSTIMER_CONF_REG(s0)
    li t1,0x40000000
    sw t1,SYSTIMER_UNIT0_OP_REG(s0)
1:                                      # loop
    lw t1,SYSTIMER_UNIT0_OP_REG(s0)
    li t2,0x20000000
    and t1,t1,t2
    beqz t1,1b
    lw t2,SYSTIMER_UNIT0_VALUE_LO_REG(s0)
    lw t3,SYSTIMER_UNIT0_VALUE_HI_REG(s0)   # lit le compteur actuel
    affregtit compteurdebut
                                            # TODO:  verifier le depassement de 32 bits
   # li t1,0x80000000
    sw x0,SYSTIMER_TARGET0_CONF_REG(s0)     # mode alarme simple et compteur 0
    li t1,8000000  * 5                      # temps attente 5s, 2 cycles pour 16 mhz
    add t2,t2,t1
    sw t2,SYSTIMER_TARGET0_LO_REG(s0)       # maj des compteurs
    sw t3,SYSTIMER_TARGET0_HI_REG(s0)
    affregtit compteurcibles
    
    li t1,1
    sw t1,SYSTIMER_COMP0_LOAD_REG(s0)       # recopie compteurs
    
    lw t5,SYSTIMER_CONF_REG(s0)
    li t2,0x1000000
    or t5,t5,t2                             # active la comparaison 
    sw t5,SYSTIMER_CONF_REG(s0)
    
    li s1,INTMTX
    li t1,1                # voir table 10.3.1    interrupt 1
    sw t1,INTMTX_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG(s1)


    li s2,INTPRI
    li t1,5                            # priorite
    sw t1,INTPRI_CORE0_CPU_INT_PRI_1_REG(s2)
    li t1,0b10                         # interruption 1
    sw t1,INTPRI_CORE0_CPU_INT_ENABLE_REG(s2)
   # sw t1,INTPRI_CORE0_CPU_INT_TYPE_REG(s2)    # or 1 ???
    /*    utility ??????
    li t1,1
    sw t1,INTPRI_CPU_INTR_FROM_CPU_0_REG(s2)
    sw t1,INTPRI_CPU_INTR_FROM_CPU_1_REG(s2)
    sw t1,INTPRI_CPU_INTR_FROM_CPU_2_REG(s2)
    sw t1,INTPRI_CPU_INTR_FROM_CPU_3_REG(s2)
    */
    
    li t1,1                                 # autorise interruption
    sw t1,SYSTIMER_INT_ENA_REG(s0)
    sw t1,SYSTIMER_INT_CLR_REG(s0)
    sw x0,SYSTIMER_INT_CLR_REG(s0)
    
    fence

    li t0,0b10                         #  enable interrup 1
    csrrw   zero, mie, t0

2:                                     # loop end system counter
    lw t1,SYSTIMER_INT_ST_REG(s0)
    andi t1,t1,1
    beqz t1,2b
    
    afficherLib finALARME
    lw t4,SYSTIMER_UNIT0_OP_REG(s0)
    affregtit timersysteme
     li t1,0x40000000
    sw t1,SYSTIMER_UNIT0_OP_REG(s0)
3:                                       # loop wait read counter
    lw t1,SYSTIMER_UNIT0_OP_REG(s0)
    li t2,0x20000000
    and t1,t1,t2
    beqz t1,3b
    lw t2,SYSTIMER_UNIT0_VALUE_LO_REG(s0)  # to verify end counter
    lw t3,SYSTIMER_UNIT0_VALUE_HI_REG(s0)

    
    affregtit timersysteme
    lw t0,INTMTX_CORE0_INT_STATUS_0_REG(s1)
    lw t1,INTMTX_CORE0_INT_STATUS_1_REG(s1)
    lw t2,INTMTX_CORE0_INT_STATUS_2_REG(s1)
    lw t4,SYSTIMER_UNIT0_OP_REG(s0)
    lw t5,INTPRI_CORE0_CPU_INT_EIP_STATUS_REG(s3)
    
    csrr   t6, mcause
    csrr   a0,misa
    csrr   a1,mideleg
    csrr   a2,mip
    affregtit statusint          # to verify all register 
    
100:    
    lw      ra, 0(sp)
    addi    sp, sp, 8
    ret 

and the final content of the registers:

Affichage registres : statusint

gr : 00000000 t0 : 00000000 t1 : 02000000 t2 : 00000000 t3 : 00000002
t4 : 20000000 t5 : 00000000 t6 : 80000003 a0 : 40903105 a1 : 00000111
a2 : 00000000 a3 : 00000000 a4 : 00000100 a5 : 42000008 a6 : 00000000
a7 : 00000010 s0 : 6000A000 s1 : 60010000 s2 : 600C5000 s3 : 40880000
s4 : 0000000A s5 : 00000002 s6 : 0000000F s7 : 00000000 s8 : 00000000
s9: 00000000 s10: 00000000 s11 : 00000000 ra : 4200094A sp : 4080CBF8

Thanck.