Can the output current of the esp32 GPIO be reduced?
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Neuer_User
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- Joined: Tue Apr 16, 2019 3:28 pm
Re: Can the output current of the esp32 GPIO be reduced?
Thanks. If it is fine for the esp32 I will use it as is for the time being. I plan to develop a second version some time later, which should have additional peripherals on an external pcb and I will add a FET there then.
Re: Can the output current of the esp32 GPIO be reduced?
What will happen if i set the drive strength of a pin output to 20mA and the load will be 50mA?
Re: Can the output current of the esp32 GPIO be reduced?
If you're driving a MOSFET, especially at a frequency (e.g. PWM), I'd really recommend using a MOSFET gate driver. They can supply up to several amperes to charge/discharge the gate of a power MOSFET in time. They're dead cheap and can also be used for driving relays. In some cases you can leave out the power MOSFET altogether.
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MicroController
- Posts: 2705
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Re: Can the output current of the esp32 GPIO be reduced?
The impedance ("resistance") of the output (~50-100Ohms) becomes significant, causing the voltage put out on the pin to drop below the specified "high" output voltage (or rise above the specified "low" output voltage). The ESPs appear to be pretty robust however; I saw some spec (for the S3, IIRC) which reported no failure after 24 hours of running with "high" outputs short-circuited to GND. (Obviously not recommended or guaranteed as this exceeds the specified maximums.)What will happen if i set the drive strength of a pin output to 20mA and the load will be 50mA?
Re: Can the output current of the esp32 GPIO be reduced?
I always treated the ESP32 drive strength as signal “slew-rate” control.
That is, control the rise and fall times of the gpio transitions, espescially to meet timing requirements of attached devices. Higher “slew-rate” means faster rise/fall times. This is an AC transient, and in my opinion, not in any way a steady-state DC specification.
The primary use-case for adjusting drive strengh is:
A. Increasing drive strength to increase “slew-rate” to meet timing specs into a problematic wire capacitance.
B. Decreasing drive strength to decrease “slew-rate” to reduce radiated noise (EMI, FCC …).
I design a single gpio to handle no moe than 20 mA DC, regardless of the datasheet. A single LED pulling more than 20 mA or more is a special case of - oh well it works fine. Other logic chips should not pull large currents.
When there is more than one gpio at higher currents, then all thermal consierations become a concern.
The internal drivers of an ESP32 might have some sort of DC level control, but I have not proved it myself.
And I certainly made up the 20 mA number, but don’t think of your hot power-hungry SOC as a H-bridge motor driver.
Burtrum
That is, control the rise and fall times of the gpio transitions, espescially to meet timing requirements of attached devices. Higher “slew-rate” means faster rise/fall times. This is an AC transient, and in my opinion, not in any way a steady-state DC specification.
The primary use-case for adjusting drive strengh is:
A. Increasing drive strength to increase “slew-rate” to meet timing specs into a problematic wire capacitance.
B. Decreasing drive strength to decrease “slew-rate” to reduce radiated noise (EMI, FCC …).
I design a single gpio to handle no moe than 20 mA DC, regardless of the datasheet. A single LED pulling more than 20 mA or more is a special case of - oh well it works fine. Other logic chips should not pull large currents.
When there is more than one gpio at higher currents, then all thermal consierations become a concern.
The internal drivers of an ESP32 might have some sort of DC level control, but I have not proved it myself.
And I certainly made up the 20 mA number, but don’t think of your hot power-hungry SOC as a H-bridge motor driver.
Burtrum
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