Documentation Requests/Feedback

michprev
Posts: 92
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sat Nov 17, 2018 5:41 pm

AFAIK there is also bug in WP settings (https://github.com/espressif/esp-idf/bl ... ruct.h#L56) both with user commands and SPI flash commands.

michprev
Posts: 92
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sun Nov 18, 2018 10:02 am

michprev wrote:
Sat Oct 20, 2018 11:33 am
  • [SPI] CS setup time does not work in full duplex
I don't think you realise how huge problem this is. Full-duplex is the most common setup and most SPI peripherals require CS active several clocks before the data transfer.

michprev
Posts: 92
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sun Nov 18, 2018 9:22 pm

https://github.com/espressif/esp-idf/bl ... #L382-L438 this is not documented

And what does this mean? https://github.com/espressif/esp-idf/bl ... #L843-L846
Is it the same issue as the one above?

michprev
Posts: 92
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sat Nov 24, 2018 3:58 pm

Setting SPI_CLKCNT_H too high in SPI_CLOCK_REG register makes in some cases (probably depending on SPI_CLKCNT_N) stop SPI working. This is not documented.

michprev
Posts: 92
Joined: Fri Aug 04, 2017 8:57 pm

Re: Document Requests

Postby michprev » Sun Nov 25, 2018 8:43 am

https://docs.espressif.com/projects/esp ... own-issues
Half duplex mode is not compatible with DMA when both writing and reading phases exist.
What does it mean exactly? When SPI_DOUTDIN in SPI_USER_REG is set to zero this issue occurs?

ESP_Lvxinyue
Posts: 33
Joined: Fri Dec 25, 2015 6:13 am

Re: Document Requests

Postby ESP_Lvxinyue » Tue Nov 27, 2018 6:24 am

michprev wrote:
Sun Nov 18, 2018 10:02 am
michprev wrote:
Sat Oct 20, 2018 11:33 am
  • [SPI] CS setup time does not work in full duplex
I don't think you realise how huge problem this is. Full-duplex is the most common setup and most SPI peripherals require CS active several clocks before the data transfer.
In full-duplex mode, setting SPI_CS_SETUP results in 1.5 SPI clock cycles between CS active and data transfer, while clearing this bit results in half an SPI clock cycle in between.

ESP_Lvxinyue
Posts: 33
Joined: Fri Dec 25, 2015 6:13 am

Re: Document Requests

Postby ESP_Lvxinyue » Tue Nov 27, 2018 6:26 am

michprev wrote:
Sat Nov 24, 2018 3:58 pm
Setting SPI_CLKCNT_H too high in SPI_CLOCK_REG register makes in some cases (probably depending on SPI_CLKCNT_N) stop SPI working. This is not documented.
PI_CLKCNT_H=⌊SPI_CLKCNT_N+1/2 – 1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L

pa_denizen
Posts: 2
Joined: Mon Feb 04, 2019 7:52 am

Re: Document Requests/Feedback

Postby pa_denizen » Mon Feb 04, 2019 8:11 am

Hi,

I was wondering if there was an inconsistency in the documentation with respect to the ADC1 channel mappings. Here is what I see from the latest docs:

page 34 of esp32_datasheet_en.pdf V2.8:

ADC1_CH0 SENSOR_VP
ADC1_CH1 SENSOR_VN
ADC1_CH2 SENSOR_CAPP
ADC1_CH3 SENSOR_CAPN

Notice that ADC1_CH3 is SENSOR_CAPN and ADC1_CH1 is SENSOR_VN.

On page 14 of the same doc:

SENSOR_VP 5 I GPIO36, ADC1_CH0, RTC_GPIO0
SENSOR_CAPP 6 I GPIO37, ADC1_CH1, RTC_GPIO1
SENSOR_CAPN 7 I GPIO38, ADC1_CH2, RTC_GPIO2
SENSOR_VN 8 I GPIO39, ADC1_CH3, RTC_GPIO3

Notice that ADC1_CH3 is now SENSOR_VN and ADC1_CH1 is SENSOR_CAPP. Also SENSOR_CAPP is also not consistent.

I think that the latter definition is correct, but can someone check and confirm this?

ESP_Lvxinyue
Posts: 33
Joined: Fri Dec 25, 2015 6:13 am

Re: Document Requests/Feedback

Postby ESP_Lvxinyue » Tue Feb 12, 2019 2:44 am

pa_denizen wrote:
Mon Feb 04, 2019 8:11 am
Hi,

I was wondering if there was an inconsistency in the documentation with respect to the ADC1 channel mappings. Here is what I see from the latest docs:

page 34 of esp32_datasheet_en.pdf V2.8:

ADC1_CH0 SENSOR_VP
ADC1_CH1 SENSOR_VN
ADC1_CH2 SENSOR_CAPP
ADC1_CH3 SENSOR_CAPN

Notice that ADC1_CH3 is SENSOR_CAPN and ADC1_CH1 is SENSOR_VN.

On page 14 of the same doc:

SENSOR_VP 5 I GPIO36, ADC1_CH0, RTC_GPIO0
SENSOR_CAPP 6 I GPIO37, ADC1_CH1, RTC_GPIO1
SENSOR_CAPN 7 I GPIO38, ADC1_CH2, RTC_GPIO2
SENSOR_VN 8 I GPIO39, ADC1_CH3, RTC_GPIO3

Notice that ADC1_CH3 is now SENSOR_VN and ADC1_CH1 is SENSOR_CAPP. Also SENSOR_CAPP is also not consistent.

I think that the latter definition is correct, but can someone check and confirm this?
Hi,

Thanks for pointing it out. The information in the Pin Description table on page 14 is correct. The documentation team will fix the inconsistency.

chibill
Posts: 10
Joined: Wed Mar 27, 2019 2:48 pm

Re: Documentation Requests/Feedback

Postby chibill » Wed Mar 27, 2019 2:51 pm

I would like too request documentation of the SDR like part of the ESP32 core. (Specifically the two High speed DACs and ADCs used in quadrature to form the 2.4 Ghz Radio.)

The only mention of them is the Technical docs. And only mention their existence and now how they are connected or how to use them.

https://www.espressif.com/sites/default ... pdf#page24

Sections 3.4.1 and 3.4.2

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