espressif's "Chip7 2-2-A" spotted in the wild

[rudi ;-)]

07 2019 - June 2019 ?

week 7 of year 2019 was production

best wishes
rudi

[rudi ;-)]

what we know about:

a) in this version there is no 5 GHz but it is on the work

b) in this version is USB

c) TinyBASIC port in ROM?
no in this not but there is plan 4 versions of based on the new architecture

d) it is a Tensilica / RISC V are in the pipelines.

e) there are beta user / request possible

f) there is no CAP1 and CAP2 any more



...still in edit work this post ...

best wishes
rudi

[WiFive]

Any bets on
usb rom bootloader
Encrypted psram
Improved adc
Battery backed rtc

[Vader_Mester]

Not quite sure looking at picture - but is the chip size 2x bigger?
More cores? )

Well, in the ESP32, 75% of the chip size is the RAM And that is just a 2mmx2mm silicon die. So I'm guessing the bigger chip size is mostly due to it having more RAM, and more IOs. More cores and stuff can just fit nicely on the same space as it currently occupies on the ESP32.

[rudi ;-)]

@WiFive
today was FCC alert with ESP32 and ESP8285

the last named is a new modul design based at ESP8285 - it looks like "usb" for flashing, booting (SDIO ) and so on

ESPWROOM5C_NEW_PCB_Design.jpg (90.15 KiB) Viewed 2807 times

I can imagine that here cnlohr's USB1.1 will be running or I even say, that it was explicitly intended (Test series)

best wishes
rudi


edit: only typo

[Vader_Mester]

Any bets on
usb rom bootloader
Encrypted psram
Improved adc
Battery backed rtc

And possibly USB host mode? Would be nice, to hook up a LAN9415 to it

[rudi ;-)]

also:
ESP32-EYE
the ESP32-D0WD is on left and right side 14 pins and top and bottom 10 pins

ESP32D0WD_5.5.jpg (83.22 KiB) Viewed 2800 times

so if we compare this Chip with Chip7 possible size

ESP32-D0WD.jpg (150.16 KiB) Viewed 2800 times

i think it can be not to be so much bigger be the chip7

compare_not_100_procent_scaled!_only_for_eye_view.jpg (273.3 KiB) Viewed 2800 times

he looks thicker (higher)
perhabs we have an port expander eMbedded for more GPIO pins and "coded" USB instead Cap1 Cap2 .. so or so ..


best wishes
rudi

[chromebin]

Just to temper expectations a bit: this is likely not going to be the top-of-the-line powerhouse that you guys think/hope it will be, as seen in the posts in this topic. Not saying we're not working on one of those but this is not it. (It does have a few picks from the ideas of the 'what would you like to see in the new chip' topic inside, though.)

What we need is a workhorse, a better allrounder than the ESP32 is, at roughly the same price. Seems like it is.

Congratulations on using RISCV: cheaper, higher clocks, lower power, Rust support and an easy upgrade path.

If it delivers this chip might become everybody's preferred micro-controller, a blockbuster.

Tiny basic? A WebAssembly _interpreter_ would let us to download and then run code from many languages, dynamically.

[fly135]

It was previously posted by an ESP engineer here that more cores weren't in the planning for the current chip because memory bandwidth would make them pointless.

John A

[The_YongGrand]

I hope there's vector operations/instructions for this - it'll be easier to handle complex numbers and some graphics too.