where the xtensa CPU vector entry point address definition ?

[caozilong]

i meet a crash in the point of "_WindowOverflow4", i try to find the XEA2 xtensa exception entry definition from the xtensa spec, but cant found the exception vector entry defition like other ISA like arm (0xffff0000) and mips(0xbfc000000) etc
so, any body can tell me how the xtensa cores exception vector definition?
thank you!

[ESP_Sprite]

Xtensa has a CSR called VECBASE to indicate the position of these. However, if you have a crash in the WindowOverflow4 interrupt, there'sa high likelyhood you're doing something terribly wrong with stack memory. (Alternatively, you're doing something wrong with high-level interrupts.)