GPIO interrupts lost (hardware race condition)

[ybuyankin]

In my case, level interrupts are not quite useful as my hardware requires SPI command to clear the IRQ signal and the SPI is not working inside the handler so that's truly awkward. My workaround still works fine for me though, thank you!

For your question (sorry I missed it) yest that's the case, but only thing slightly different is that this condition happens only when the second IRQ comes exactly at the moment (same clock cycle likely) when the thirst one gets cleared (because of register writes conflict I guess). In your picture clearing occurs noticeably later than the second IRQ comes, in that case everything goes fine.