ESP32 Forum

(How) do you send a BREAK to reset/synchronize?

This question doesn't seem to be related to the seven year old thread you resurrected.

Your question seems to be "how do I send a break", which isn't really appropriate in the hardware group at all, but it's documented in ESP-IDF.

uart_write_bytes_with_break() is covered in many places, but notably https://docs.espressif.com/projects/esp ... /uart.html

When it's time to receive one, you'll get a UART_BREAK event, as described at https://docs.espressif.com/projects/esp ... /uart.html

If a follow-up is necessary, I'd suggest doing so in a new thread, after searching existing threads, and including a short, self-contained, stand-alone ESP-IDF program where you can demonstrate a use of uart_write_bytes_with_break() not sending a break. I suspect it won't be necessary, but ESP-IDF hasn't always been bug-free in this area as BREAKs are pretty uncommonly used these days.


In fact, they'd be completly unusable in the context this was originally asked because you need one sender and one receiver and that needs to be negotiated externally to the communication itself.

This question doesn't seem to be related to the seven year old thread you resurrected.

Your question seems to be "how do I send a break"...

Well, no. My question is if and how @realfspin does send a BREAK as required by the UPDI protocol he's struggling to get running

Just to be clear, the original advice about open drain helped me significantly which was indeed related to the thread.

But yes, discussing the updi break is probably outside the scope of this thread. Although, I wonder if maybe RandomInternetGuy fell prey to the pagination and opened this 7 year old thread only to see your post (first of page 2) asking how to send a break to reset synchronize

Anyway, when I snoop on jtag2updi and I use the hardware uart listener I do actually receive something like 0x00 0x00 0x55 ... where the first two bytes appear to be a double break as per updi spec, and then followed by a 55 and a updi command which matches the source code of jtag2updi.

All of this said, I have made significant progress and acquired a cheap digital scope to look at my signal and I think I've been able to pinpoint several more problems, one was in my break length, and the other seems to be in my ability to bitbang a square signal.

I am still having issues but I feel that my issues probably belong in a new thread at this point. I will continue the discussion here:

https://esp32.com/viewtopic.php?f=13&t=40073

Although, I wonder if maybe RandomInternetGuy fell prey to the pagination and opened this 7 year old thread only to see your post (first of page 2) asking how to send a break to reset synchronize

Definitely The board software takes no prisoners

So, after further investigation, I believe the issue is still line contention even with the code given before.

I believe this is back on track with the thread purpose, a combined rx/tx line that alternates between rx and tx.

Is there anything we are missing with the uart initialization or control?

Another idea: The internal pull-up of the ESP (~50k) may be a bit weak. You can try adding an external pull up resistor, 5-10k maybe, to try and improve the signal quality.

well I've given up and fallen back on bitbanging, seems that using a bit timing of 200us has worked, maybe other timings work too.

I think the problem is the tx line was holing the line HIGH so the attiny couldn't respond and pull the line low.

I'm sure it's possible with the hardware uart but from what I can see I have it working and I would rather not waste more time.

Thanks guys