ESP32 Forum

I just ran into this same issue this weekend. With my config, you cannot program the esp32 while the clock (50MHz which comes from the phy) is connected to GPIO0. It is strange that this GPIO was chosen for the clock input. I'm currently (manually) killing power to the phy until the esp32 has booted. Note that the EMAC continuously resets without the clock signal applied (emac: emac reseting ....).

Another issue I'm seeing while doing a packet trace on the DHCP server is that it receives the DHCP request, responds, but the esp32 doesn't seem to get the response (based on IP zero'd out in printout of ethernet sample program). I'm digging into the library now.

I'm using the microchip LAN8720A phy ($0.94 in quantity) vs the TLK110 phy ($3.34 in quantity).

前面网友说的加一个时钟使能管脚貌似可以解决这个问题，但是esp32管脚本来就紧张又需要额外浪费一个管脚，而且理论ok，实际上还是有时钟未停止esp就启动的风险

还有一个解决思路是，使用esp32自身的emac时钟，使用gpio16，不过没有官方代码，不知道如何配置

还有一个解决思路是，使用esp32自身的emac时钟，使用gpio16，不过没有官方代码，不知道如何配置

hi

yeah - this was the plan


https://github.com/espressif/esp-idf/bl ... _reg.h#L24
https://github.com/espressif/esp-idf/bl ... dev.c#L104
https://github.com/espressif/esp-idf/bl ... dev.c#L138

we puzzle here , want ping at weekend - hope we figure it out do weekend.
there are no documents online - esp guys remain silent


best wishes
rudi

I have the same problem.Now I can use GPIO16 to generate 50MHZ clk for PHY. But in new module ESP-WROVER use GPIO16 and GPIO17 for PSRAM,How disappointing!
olimex havd a new board,it use delay CMOS to deal this problem.Is there a suggested solution for Espressif ??

I have the same problem.

Now I can use GPIO16 to generate 50MHZ clk for PHY.
But in new module ESP-WROVER use GPIO16 and GPIO17 for PSRAM,How disappointing!

olimex havd a new board,it use delay CMOS to deal this problem.Is there a suggested solution for Espressif ??

this are 2 different things from where you speak:

a) IO16, IO17 is used as CS and CLK for pSRAM in wrover and is not availaible for other cause it is not ledout
so you can't use IO16 as signal for your phy


b) generated clk signal for PHY on IO16 get a delay to can boot the module cause this signal goes to IO0 and is bootstrap
but use 50Mhz OSZ on board to generate 50MHz clk for phy that goes to IO0

...

what you want to do?
what you want to change?


best wishes
rudi

It might be possible to still provide phy clock source from esp32 using apll and i2s clk_out pin

Hi rudi !
Now I plan to use IO0 to do it.

Hi rudi !
Now I plan to use IO0 to do it.

i am not sure you can use IO0 for "generating" the 50Mhz signal that comes then on IO0 as PhyCLK
..but yes - IO0 is for the PHY CLK input

hope this helps
best wishe
rudi