ESP32 Forum

I was wondering if you have used the "use_apll" feature to get a more accurate sampling clock as suggested in the IDF instructions. This is for the i2S configuration. When I set this to "true" the APLL clock message does show that the requested rate and real rate are virtually identical. However the data captured seems to be at 16 times the set rate. For example, setting the sampling rate to 32000 I captured 512 samples of a 1 kHz sine wave. This should have 16 cycles when plotted. Instead I get just one period - and that too with a lot of jitter!


Thanks.

I tried to run the attached file in platformio and I couldn't because the dig_i2s_adc library is missing, I saw that a .h and a .c file is included I tried to add them to the lib folder of my platformio project and I couldn't. any suggestion?

cannot convert 'adc1_channel_t' to 'adc_channel_t' in initialization
this error is showing while running the code