ESP32 Forum

Yes. THe default pullups and -downs are documented in the pin list document: https://espressif.com/sites/default/fil ... t_en_0.pdf

Great. Then I will not add them to the schematic. Does save some PCB space.

On the subject of strapping pins, there's one other note from Technical Reference manual section 4.8.1 worth mentioning:

The VDD_SDIO voltage can be configured to be either 1.8V or 3.3V (the same as that at VRTC), depending on the state of the MTDI pad at reset - a high level configures 1.8V and a low level configures 3.3V.

VDD_SDIO is the voltage used for the SPI flash access. MTDI pin defaults to pulled down (ie unless driven high, the ESP32 is configured for 3.3V flash.)

Hi,

Can anyone tell me when the strapping pin values are actually latched in?
Is it on the rising edge of the EN pin?

Maybe a better question is...
Can anyone provide a timing diagram for the strapping pins?
To include the set up and hold times for the strapping bits and EN pin?

I'm building a new board and want to allow setting the strapping bits dynamically and then hitting the reset button to reboot the processor into a different strapping mode. I'm using an 8 bit buffer and want to use the reset (EN) signal to switch the strapping jumpers on and off the pins of the processor. I.e. when the reset/EN pins goes low, the buffer will pass the strapping jumpers onto processor pins. When reset/EN goes high the buffer will tri state and I can use the IOs for what ever I want without having any PU and PD resistors on them.

But I don't know the timing on the strapping pins and don't want to fab a board without understanding the possible timing variance on these pins.

Anyone have any info on this they can share?

Thanks
TT

The EN line is not a 'classical' reset as you seem to assume. What it actually does is physically power down all the power domains in the chip, and pulling it low is in some way equivalent to removing the power from the chip. Hence, if you make it high, all the normal power-on things kick in: the power-on reset activates, the crystal oscillator starts up, and after the crystal oscillator is stable, the bootstrap pins get sampled. Usually, that takes a ms or so, but I assume it will vary with the crystal specifics.

Thanks
That helps a lot.

Does EN also disable the power rail for the ultra low power core?