ESP32 Forum

update:
=======


Hi Folks,

please correct me if the assumption is not correct.
ESP32C5beta3 is preview supported in ESP-IDF V5.3 and ESP32-C5 MP will be supported in ESP32-IDF V5.4
which contains the ESP32-C5N, ESP32-C5NR4 ESP32-C5NF4, ( ESP32-C5-WROOM-1 MAN8R4) , ESP32-C5-DevKitC1-N8R4 )

Current status of ESP32-C5 MP support, the career is continued here by Ivan. I'm not quite sure if we can still use ESP-IDF V5.3 or V5.3.1 for the ESP32-C5-DevKitC (Chip V0.0) or if we have to switch to the ESP-IDF-V5.4 dev and can still use the ESP32-C5Beta3.

In any case of uncertainty : Create a new folder (Fun, maybe someone can add the correctness)

btw: the SoC on a fresh PCB want's a FW

best wishes
rudi

edit: I forgot to mention that we unfortunately don't have ESP32-C5 MP support "public" yet or did I not notice something or even missed it?

edit: typo

update:


Hi Folks,

i use for a fast test ESP-IDF V5.3 with preview support for the ESP32-C5 MP

your friend is:
idf.py --preview set-target ESP32C5

cause we can set 40 MHz / 48 MHz crystal for the ESP32-C5 in the Code / ESP-IDF ( used 48 MHz here ) so the bootloader works well at 115200 but not in the app code - you need to set the baudrate by your self in the ESP-IDF V5.3

i use for the used 48 MHz crystal a Baudrate of 138240 this should be in the ESP-IDF V5.3 a standard

( check then the menuconfig for switching to ESP32-C5 MP )
( you can use a custom uart too if you use an 40 MHz crystal - i have not checked this by code yet hope you get the idea behind )

save, build, flash and volla :

this helps for the ESP32-C5 MP if you use the preview support ESP-IDF V5.3
now i am waiting for the ESP-IDF V5.4

WoWZa !

best wishes
rudi

update:
======

I was asked in XDM how I know this. no insider tip sry
If you use the V5.3 you find the hint in the ESP-IDF V5.3 Code to use 138240 baud for the ESP32-C5 and 48MHz"

If you are one of the lucky few who were able to get some from ESPRESSIF Official Store ( Aliexpress ) / or Espressif Sales
this Baudrate can be also used for the ESP32-C5-DevKitC-1, so i think 48Mhz is used in the DevKit which comes with Sample V0.0 Chip.

( Hint M5Stack posted in July a ESP32-C5 prototype. From picture it is used 48MHz crystal, and you see the new one with QFN48 , and traces to follow your design, btw you find all infos around the world, you simple have to catch them )

Use 138240 in your serial connection ( putty .. or anything you use )
and you see the bootlog. Don't be alarmed at 138240, the stage 1 is cryptic, but the app code is readable. Reversed 115200 the stage 1 is readable for the bootloader e.g. hope this helps, i think docu is not ready for this yet.

Stay tuned

best wishes
rudi

update
======
Hi Folks


just want update this
ESP32-C5-DevKitC-1 N8R4 from aliexpress ESPRESSIF Official Shop is here
soldered is ESP32-C5-WROOM-1 ( MAN8R4 )
ccontains:
Sample Chip V0.0
- MCU SoC ESP32-C5 NR4 ( 4 MB inside packed )
- external 8 MB Flash

picture says more best wishes
rudi

edit: add snippet from iperf splash boot picture

update
=======


Hi Folks
what is known so far is the description of this thread so
i upload now this - you are updated what is known so far.

That also explains one or the other



....there can be nothing hidden!


best wishes
rudi


edit : "the antenna looks mirrored inverted"

update
=======
Hi Folks,

someone must have taken the trouble to edit the image of the antenna with emboss / relief filter also to disguise parts of the lettering around the antenna structure, so bad that it almost borders on common sense. I think the perpetrator was convicted There is only one version.

A comparison of the manipulated image to an original and recursive filtering made the "fraud" visible. (to be seen in the video) Why do people do this?



There are also good news :
Further ESP32-C5-DevkitC-1 spotted in the wild

best wishes
rudi

Hi Folks

At the moment I'm very busy with the C5.
The little one is amazingly good and at the same time you expect more and more and go into areas that are not yet covered and bump into things here and there. (When is the MP time coming - I want more, we are eagerly waiting for it )

After breaking firmware and time-consuming checking and testing, I have created my own small program specially tailored to the C5 on the desktop of a tried and tested IDE since my youth in order to test recurring processes more quickly. You find a screenshot bottum attached, If there is interest in the program, I can also upload it, the created FW image goes to the **knowed repos**

A small video was created for this - which was uploaded to the ESP32 channel, if you are interested you can find it here. Nothing special, just shows that 5G works as far as the current state is concerned. A bit of a color spruce up - but that's not really my thing - I mostly just focus on the functionality - hope it meets the general mainstream requirements

As I also encountered various problems with the preview factory firmware and the example iperf did not compile as desired with my installed version of ESP-IDF V5.3-dirty / ESP-IDF V5.4-dirty, the wifi-binary lib and extra adjustments etc., after some advice from espressif support (many thanks at this point) I jumped to the ESP-IDF Master with the current status and version ESP-IDF V5.4-dev-2744-g59e1838270-dirty for this experiment, and I have to say, it helped me to deal with the problems and compile the iPERF firmware after adjustment.

Flashed onto two ESP32-C5-DevKitC-1 and various design PCBs (working so far), I was able to test various things via iPERF that I hadn't been able to do with the factory FW at first, but I am also entitled to apologize and deny blame, as it was a very early stage of development and not all areas that the C5 makes available were covered.

With the current state of things, I was able to test more than before and successfully. Cross-country setups are now possible and work so far. The 5G mode started in my area with 20MBit/s and passed the iPERF test without any problems, there is still potential and I am very interested in further testing and performance improvements, which are certainly far from over at this point in time and in this environment.

- PSRAM support? Yes
- WiFi 2.4 / 5.8? Yes
- 5G AP possible? Yes
- 5G STA possible? YES
- Can the AP be scanned by STA? YES
- Can it also find other AP? Yes
- Can the STA join the AP? Yes
- Country support? Yes

There's still a lot more to be done

Next week it will be a bit quieter because of the upcoming Mid-Autumn Festival and next week we'll go into more detail and the interaction between firmware and PCB and the DevKits. I'm really curious to see how it goes. There will definitely be more PCB designs for various occasions and tests. I'll write a thread about this in the hardware section that might be of interest to some people and then share my findings here and also in the target project there **knowed repos**.

If you got an Kit be sure to use 138240 baud instead 115200 in this version with putty or any other TERMprog
this is temporally a need casued a *bit mistake in the efuse* and using 48MHz crystal on this kits / SoC

Wish you a happy mid-autumn (中秋节) festival in advance if we not read/write next days
greetings fly out to friends all over the globe
best wishes
rudi

edit: append info baud and things what was tested

Hi Folks,

update:
======


According to the chip mass production plan, the planned support for ESP32-C5 in ESP-IDF v5.4 has been rescheduled to ESP-IDF v5.5.

ESP-IDF v5.5, whose planned release date is June 30th 2025, will include the initial support for the mass production version of ESP32-C5.

best wishes
rudi

update
======


hi folks,

the c5 soc , the C5 Modul and C5 DevKit now public as samples, get in contact with sales directly and grab it quickly while they are still available.

FYI: watch the nice video about the 5.8GHz from Andreas Spiess ( the guy with the Swiss accent )
best wishes

update
======


Hi Folks,

Espressif announce that ESP32-C5 is now in mass production.
great news, right?

Just boot an ESP32-C5-DevKitC1 from espressif aliexpress shop


ESP-ROM:esp32c5-eco2-20250121
Build:Jan 21 2025
rst:0x1 (POWERON),boot:0x8 (DOWNLOAD(UART0/USB))
waiting for download


ESP32-C5 ECO2 is here ( ESP32-C5-WROOM-1 N8R4 V1.3 DEV-KIT-C- V1.2 ).
It's real!

However, the chip revision: v1.0 for ECO2 is a bit confusing


ESP-ROM:esp32c5-eco2-20250121
Build:Jan 21 2025
rst:0x1 (POWERON),boot:0x8 (DOWNLOAD(UART0/USB))
waiting for download
ESP-ROM:esp32c5-eco2-20250121
Build:Jan 21 2025
rst:0x1 (POWERON),boot:0x18 (SPI_FAST_FLASH_BOOT)
SPI mode:DIO, clock div:1
load:0x408556b0,len:0x1784
load:0x4084bba0,len:0xd78
load:0x4084e5a0,len:0x30cc
entry 0x4084bbaa
I (23) boot: ESP-IDF v5.5-dev-3506-g0973d2b4b6e-dirt 2nd stage bootloader
I (24) boot: compile time May 6 2025 21:00:47
I (24) boot: chip revision: v1.0
I (26) boot: efuse block revision: v0.2
I (29) boot.esp32c5: SPI Speed : 80MHz
I (33) boot.esp32c5: SPI Mode : DIO
I (37) boot.esp32c5: SPI Flash Size : 2MB
I (41) boot: Enabling RNG early entropy source...
I (45) boot: Partition Table:
I (48) boot: ## Label Usage Type ST Offset Length
I (54) boot: 0 nvs WiFi data 01 02 00009000 00006000
I (60) boot: 1 phy_init RF data 01 01 0000f000 00001000
I (67) boot: 2 factory factory app 00 00 00010000 00100000
I (74) boot: End of partition table
I (77) esp_image: segment 0: paddr=00010020 vaddr=42020020 size=08a3ch ( 35388) map
I (91) esp_image: segment 1: paddr=00018a64 vaddr=40800000 size=075b4h ( 30132) load
I (98) esp_image: segment 2: paddr=00020020 vaddr=42000020 size=16fd4h ( 94164) map
I (115) esp_image: segment 3: paddr=00036ffc vaddr=408075b4 size=0372ch ( 14124) load
I (119) esp_image: segment 4: paddr=0003a730 vaddr=4080ad00 size=016c4h ( 5828) load
I (123) boot: Loaded app from partition at offset 0x10000
I (124) boot: Disabling RNG early entropy source...
I (141) cpu_start: Unicore app
W (149) clk: esp_perip_clk_init() has not been implemented yet
I (154) cpu_start: Pro cpu start user code
I (155) cpu_start: cpu freq: 240000000 Hz
I (155) app_init: Application information:
I (155) app_init: Project name: blink
I (158) app_init: App version: qa-test-full-v5.5-20250430-36-g
I (164) app_init: Compile time: May 6 2025 21:00:44
I (169) app_init: ELF file SHA256: d80061c73...
I (174) app_init: ESP-IDF: v5.5-dev-3506-g0973d2b4b6e-dirt
I (180) efuse_init: Min chip rev: v1.0
I (184) efuse_init: Max chip rev: v1.99
I (187) efuse_init: Chip rev: v1.0
I (191) heap_init: Initializing. RAM available for dynamic allocation:
I (198) heap_init: At 4080D2A0 len 0004F300 (316 KiB): RAM
I (203) heap_init: At 4085C5A0 len 00002F58 (11 KiB): RAM
I (208) heap_init: At 50000000 len 00003FE8 (15 KiB): RTCRAM
I (214) spi_flash: detected chip: generic
I (217) spi_flash: flash io: dio
W (220) spi_flash: Detected size(8192k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
I (232) sleep_gpio: Configure to isolate all GPIO pins in sleep state
I (238) sleep_gpio: Enable automatic switching of GPIO sleep configuration
I (245) main_task: Started on CPU0
I (245) main_task: Calling app_main()
I (245) example: Example configured to blink addressable LED!
I (71255) example: Button pressed. LED mode: 0
I (75805) example: Button pressed. LED mode: 1
I (77005) example: Button pressed. LED mode: 2
I (78105) example: Button pressed. LED mode: 3
I (79405) example: Button pressed. LED mode: 0
I (80005) example: Button pressed. LED mode: 1
I (80355) example: Button pressed. LED mode: 2
I (80705) example: Button pressed. LED mode: 3



best wishes