Re: ESP32-S31 :)
Posted: Fri Jan 09, 2026 12:41 pm
Seems like it contains no H264 codec and MIPI DPHY, the general-purpose OTG FS port has also been removed.
1. LP GPIO is reduced from 16 to 8. c.f. S3 has 22.
2. PSRAM is still at dedicated MSPI pins like P4, but reduced from HSPI (16 lines) to OSPI (8 lines).
3. Flash pins are multiplexed with normal GPIOs again so the free GPIO may need to reduce by 7 and yield the same available GPIO pins as P4. (QSPI requires 6 pins and VDD_SPI is usually used to power the flash, and those are dedicated pins on P4)
4. The 2-channel DAC gone from s3 has been revived and upgraded to 12bit (?)
.
2 DAC units, 1 2-channel 10bit DAC, and another 2-channel 12bit DAC.
5. CORDIC accelerator for advanced control, can also be found in some high-end STM32 and industrial MCUs.
6. One unit of 2-in, 2-out LP DMA in LP domain (?) can make LP app more capable.
7. HP cores have sv32 virtual memory system, capable of running (full) Linux [!!!]
Datasheet has been published
1. LP GPIO is reduced from 16 to 8. c.f. S3 has 22.
2. PSRAM is still at dedicated MSPI pins like P4, but reduced from HSPI (16 lines) to OSPI (8 lines).
3. Flash pins are multiplexed with normal GPIOs again so the free GPIO may need to reduce by 7 and yield the same available GPIO pins as P4. (QSPI requires 6 pins and VDD_SPI is usually used to power the flash, and those are dedicated pins on P4)
4. The 2-channel DAC gone from s3 has been revived and upgraded to 12bit (?)
. 2 DAC units, 1 2-channel 10bit DAC, and another 2-channel 12bit DAC.
5. CORDIC accelerator for advanced control, can also be found in some high-end STM32 and industrial MCUs.
6. One unit of 2-in, 2-out LP DMA in LP domain (?) can make LP app more capable.
7. HP cores have sv32 virtual memory system, capable of running (full) Linux [!!!]
Datasheet has been published