ESP32 Forum

Soon there will be tiny low power SoCs that may replace many MCUs unless prices drop

Which ones are you referring to?

IMPORTANT!:

If you update IDF master branch to the latest version, the Addax V1.0 boards that has the ESP32-S3(beta 3) chips are no longer supported.
Commits have been made at the beggining of June.

Latest branch that seems to supports older S3:
https://github.com/espressif/esp-idf/tr ... 9e3518a6d3

Is there anybody who owns one of the new ESP32-S3 Evalboards, who did a benchmark comparison between ESP32 and ESP32-S3?

Is there anybody who owns one of the new ESP32-S3 Evalboards, who did a benchmark comparison between ESP32 and ESP32-S3?

If you have working benchmarking code you want tested, I can do the test. I have wrover modules with ESP32 V3 chip, and S3 beta 3 modules.

Is there anybody who owns one of the new ESP32-S3 Evalboards, who did a benchmark comparison between ESP32 and ESP32-S3?

If you have working benchmarking code you want tested, I can do the test. I have wrover modules with ESP32 V3 chip, and S3 beta 3 modules.

You can find some Benchmark Code here:viewtopic.php?f=14&t=800&start=20#p73849.
But it is mainly floatingpoint related, which is probably not the most important topic for this type of uC. Nevertheless it will give an indication. It would kind if you could run this test on both ESP32 versions.
Maybe I can provide you a larger code later in order to avoid having the whole program running in cache memory.

Is there anybody who owns one of the new ESP32-S3 Evalboards, who did a benchmark comparison between ESP32 and ESP32-S3?

If you have working benchmarking code you want tested, I can do the test. I have wrover modules with ESP32 V3 chip, and S3 beta 3 modules.

You can find some Benchmark Code here:viewtopic.php?f=14&t=800&start=20#p73849.
But it is mainly floatingpoint related, which is probably not the most important topic for this type of uC. Nevertheless it will give an indication. It would kind if you could run this test on both ESP32 versions.
Maybe I can provide you a larger code later in order to avoid having the whole program running in cache memory.

OK.
What interests me is the memory usage. I will try to write benchmarking code to test memory read and write speed both for internal RAM and external SPI-RAM as well. The S3 has an improved MMU.
Also, when it will be available, I want to test code execution speed from SPI-RAM.

Rudi: I can not PM you, so if you would be so kind, to edit the first post with the following information:

Support for ESP32-S3 (beta) chips have been removed from master.
The last snapshot that supports the beta chips is this:
https://github.com/espressif/esp-idf/tr ... 9e3518a6d3

If you go into your IDF folder, and run: This will hard reset your local repo. If you made changes to it, use then This will reset your IDF back to this snapshot.

To make tools work, download the latest tools installer from here:
https://dl.espressif.com/dl/esp-idf/?idf=4.4

Then locate the folder where you have all your tools installed.
On windows machines, the default is C:\users\<username>\.espressif\tools
Detele all tools from here, EXCEPT xtensa-esp32s3-elf-gcc8_4_0-esp-2020r3-...
We need this compiler version to work best with beta chips.

Then, locate your tools.json file in your ESP-IDF directory: \esp-idf\tools\tools.json
Locate this bit, normally at line 214. (if you are running on linux then find the appropriate one for your hardware above this line).
This is the compiler tool required for the risv processors. With default settings below, tools installer will fail, because the riscv32 tool received a patch. To fix this, go to https://github.com/espressif/crosstool-NG/releases/, and from esp-2021r1, download crosstool-NG-esp-2021r1-checksum.sha256 and open in the text editor.
From your specific platform, copy the values from this file to tools.json, and edit the URL. For win64 it will be:
Sha256 file: This copied into tools.json: Once this is done, save tools.json for later to a separate location, and run the tools installer utility or install.bat from your esp-idf directory. If tools.json is correct, it will run fully, and will download all of the tools, and install them.

After the installer is finished, you should remove xtensa-esp32s3-elf-gcc8_4_0-esp-2021r1-..., so IDF will use the older one instead.
After this you are ready to go, you should do a fullclean on your project and recompile.

If you have working benchmarking code you want tested, I can do the test. I have wrover modules with ESP32 V3 chip, and S3 beta 3 modules.

You can find some Benchmark Code here:viewtopic.php?f=14&t=800&start=20#p73849.
But it is mainly floatingpoint related, which is probably not the most important topic for this type of uC. Nevertheless it will give an indication. It would kind if you could run this test on both ESP32 versions.
Maybe I can provide you a larger code later in order to avoid having the whole program running in cache memory.

OK.
What interests me is the memory usage. I will try to write benchmarking code to test memory read and write speed both for internal RAM and external SPI-RAM as well. The S3 has an improved MMU.
Also, when it will be available, I want to test code execution speed from SPI-RAM.

Yes, that is exacly what I am also interested in. This micro probalbly is mostly used for communication purposes (WiFi, BT) and in this case memory reads and writes to the various memories and fetching code from flash etc. are more relevant that floatingpoint operations. In my use case I have an application running a webserver with websocket communication. The app today has a binary size of approx. 1,5MBytes - so most of the code will be executed from ext. flash and not from cache or iram. Since my app currently is too slow I am looking forward to test the ESP32-S3.

@Vader_Mester : do you have already some Benchmark results with S3 chip?

Some DSP related benchmarks of ESP32-S3 are available here: https://docs.espressif.com/projects/esp ... marks.html.