ESP32 Forum

Code: Untitled.c Select all

/*

* Attempts to use the async_memcpy driver to copy data from one buffer to another

*

* Works for MALLOC_CAP_DMA but not if we try to align the buffers to 32 bits

* Does not work for MALLOC_CAP_SPIRAM no matter what I try.

* Reporting "invalid argument" on the call to esp_async_memcpy

*

* Using an ESP32-S3-WROOM-1U-N8R8 module

* Using the master branch of ESP-IDF cloned on 15/11/2023

* 

*/





#include <inttypes.h>

#include <string.h>



#include "malloc.h"

#include "esp_log.h"

#include "esp_heap_caps.h"

#include "esp_async_memcpy.h"



#include "freertos/FreeRTOS.h"

#include "freertos/task.h"

#include "freertos/semphr.h"



static const char *TAG = "async_memcpy";



/// @brief The source buffer

void* _source;



/// @brief The destination buffer

void* _dest;





/// @brief Async Memory copy callback implementation, running in ISR context

/// @param mcp_hdl Handle of async memcpy

/// @param event Event object, which contains related data, reserved for future

/// @param cb_args User defined arguments, passed from esp_async_memcpy function

/// @return Whether a high priority task is woken up by the callback function

static IRAM_ATTR bool my_async_memcpy_cb(async_memcpy_t mcp_hdl, async_memcpy_event_t *event, void *cb_args)

{



    // Get the semaphore handle from the callback arguments

	SemaphoreHandle_t sem = (SemaphoreHandle_t)cb_args;



    // Give the semaphore so the CPU can continue execution when its ready

    // high_task_wakeup set to pdTRUE if we want to yield to a high priority task

    BaseType_t high_task_wakeup = pdTRUE;                                   

    xSemaphoreGiveFromISR(sem, &high_task_wakeup);



    // Return whether a high priority task was woken up so the ISR knows if it needs to yield 

    return high_task_wakeup == pdTRUE;



}





/// @brief Main application entry point

void app_main(void)

{



    // Hello world

    ESP_LOGI(TAG, "\n\nasync_memcpy!\n");



    // Allocate some RAM for the source and destination buffers

    ESP_LOGI(TAG, "Allocating memory for buffers...");

    uint32_t size = 100000;

    // ** This works **

    _source = heap_caps_malloc(size, MALLOC_CAP_DMA);                                               

    _dest = heap_caps_malloc(size, MALLOC_CAP_DMA);  

    // ** This DOES NOT work **

    // _source = heap_caps_malloc(size, MALLOC_CAP_DMA | MALLOC_CAP_32BIT);                         

    // _dest = heap_caps_malloc(size, MALLOC_CAP_DMA | MALLOC_CAP_32BIT);  

    // ** This DOES NOT work **

    // _source = heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA | MALLOC_CAP_32BIT);

    // _dest = heap_caps_malloc(size, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA | MALLOC_CAP_32BIT);

    // ** This DOES NOT work **

    //_source = heap_caps_malloc(size, MALLOC_CAP_SPIRAM); 

    //_dest = heap_caps_malloc(size, MALLOC_CAP_SPIRAM);



    // Initialize the source buffer

    ESP_LOGI(TAG, "Initializing source buffer...");

    //memset(_source, 0x77, size);



    // Install the Async memcpy driver. Using the defaults + a larger backlog.

    ESP_LOGI(TAG, "Installing async_memcpy driver...");

    async_memcpy_config_t config = ASYNC_MEMCPY_DEFAULT_CONFIG();

    //uint32_t backlog = 8;

    uint32_t backlog = (size > 2500) ? size/2500 : 4;   // I think 2500 is approx the size of DMA transfer?

	config.backlog = backlog;    

    // config.sram_trans_align = 32;                    // These don't work

    // config.psram_trans_align = 32;

    async_memcpy_handle_t driver = NULL;

    //ESP_ERROR_CHECK(esp_async_memcpy_install(&config, &driver)); 

	ESP_ERROR_CHECK(esp_async_memcpy_install_gdma_ahb(&config, &driver)); 



    // Create a semaphore so we can wait for the async memcpy to complete

    ESP_LOGI(TAG, "Creating semaphore...");

    SemaphoreHandle_t semaphore = xSemaphoreCreateBinary();



    // Start the async memcpy

    ESP_LOGI(TAG, "Starting the async_memcpy to transfer %" PRIu32 " bytes...", size);

    ESP_ERROR_CHECK(esp_async_memcpy(driver, _dest, _source, size, my_async_memcpy_cb, semaphore));



    // Wait for the async memcpy to complete

    ESP_LOGI(TAG, "Waiting for the DMA operation to complete...");

    xSemaphoreTake(semaphore, portMAX_DELAY);



    // Success. All done

    ESP_LOGI(TAG, "async_memcpy complete! Transferred %" PRIu32 " bytes", size);



}

Code: Untitled.txt Select all

SPIWP:0xee

mode:DIO, clock div:1

load:0x3fce3810,len:0x178c

load:0x403c9700,len:0x4

load:0x403c9704,len:0xcb8

load:0x403cc700,len:0x2d84

entry 0x403c9914

I (26) boot: ESP-IDF v5.3-dev-277-gc8243465e4 2nd stage bootloader

I (27) boot: compile time Nov 15 2023 20:47:33

I (27) boot: Multicore bootloader

I (31) boot: chip revision: v0.1

I (35) boot.esp32s3: Boot SPI Speed : 80MHz

I (40) boot.esp32s3: SPI Mode       : DIO

I (45) boot.esp32s3: SPI Flash Size : 8MB

I (49) boot: Enabling RNG early entropy source...

I (55) boot: Partition Table:

I (58) boot: ## Label            Usage          Type ST Offset   Length

I (66) boot:  0 nvs              WiFi data        01 02 00009000 00006000

I (73) boot:  1 phy_init         RF data          01 01 0000f000 00001000

I (81) boot:  2 factory          factory app      00 00 00010000 00100000

I (88) boot: End of partition table

I (92) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0dc44h ( 56388) map

I (111) esp_image: segment 1: paddr=0001dc6c vaddr=3fc92500 size=023ach (  9132) load

I (113) esp_image: segment 2: paddr=00020020 vaddr=42000020 size=1a66ch (108140) map

I (137) esp_image: segment 3: paddr=0003a694 vaddr=3fc948ac size=00608h (  1544) load

I (138) esp_image: segment 4: paddr=0003aca4 vaddr=40374000 size=0e4b4h ( 58548) load

I (161) boot: Loaded app from partition at offset 0x10000

I (162) boot: Disabling RNG early entropy source...

I (173) cpu_start: Multicore app

I (182) cpu_start: Pro cpu start user code

I (182) cpu_start: cpu freq: 160000000 Hz

I (183) cpu_start: Application information:

I (185) cpu_start: Project name:     async_memcpy

I (191) cpu_start: App version:      d6b7f7a-dirty

I (196) cpu_start: Compile time:     Nov 15 2023 20:47:26

I (202) cpu_start: ELF file SHA256:  97614a826...

I (208) cpu_start: ESP-IDF:          v5.3-dev-277-gc8243465e4

I (214) cpu_start: Min chip rev:     v0.0

I (219) cpu_start: Max chip rev:     v0.99

I (224) cpu_start: Chip rev:         v0.1

I (228) heap_init: Initializing. RAM available for dynamic allocation:

I (236) heap_init: At 3FC95790 len 00053F80 (335 KiB): RAM

I (242) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM

I (248) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM

I (254) heap_init: At 600FE010 len 00001FD8 (7 KiB): RTCRAM

I (261) spi_flash: detected chip: generic

I (265) spi_flash: flash io: dio

I (269) sleep: Configure to isolate all GPIO pins in sleep state

I (276) sleep: Enable automatic switching of GPIO sleep configuration

I (283) main_task: Started on CPU0

I (293) main_task: Calling app_main()

I (293) async_memcpy:



async_memcpy!



I (293) async_memcpy: Allocating memory for buffers...

I (303) async_memcpy: Initializing source buffer...

I (303) async_memcpy: Installing async_memcpy driver...

D (313) gdma: new group (0) at 0x3fccbd8c

D (313) gdma: new pair (0,0) at 0x3fccbe14

D (323) gdma: new tx channel (0,0) at 0x3fccbd54

D (323) gdma: new rx channel (0,0) at 0x3fccbe34

D (333) gdma: tx channel (0,0), (0:32) bytes aligned, burst enabled

D (333) gdma: rx channel (0,0), (0:32) bytes aligned, burst disabled

D (343) gdma: install interrupt service for rx channel (0,0)

I (353) async_memcpy: Creating semaphore...

I (353) async_memcpy: Starting the async_memcpy to transfer 100000 bytes...

I (363) async_memcpy: Waiting for the DMA operation to complete...

I (373) async_memcpy: async_memcpy complete! Transferred 100000 bytes

I (373) main_task: Returned from app_main()

Code: Untitled.txt Select all

SPIWP:0xee

mode:DIO, clock div:1

load:0x3fce3810,len:0x178c

load:0x403c9700,len:0x4

load:0x403c9704,len:0xcb8

load:0x403cc700,len:0x2d84

entry 0x403c9914

I (26) boot: ESP-IDF v5.3-dev-277-gc8243465e4 2nd stage bootloader

I (26) boot: compile time Nov 15 2023 20:47:33

I (27) boot: Multicore bootloader

I (31) boot: chip revision: v0.1

I (35) boot.esp32s3: Boot SPI Speed : 80MHz

I (39) boot.esp32s3: SPI Mode       : DIO

I (44) boot.esp32s3: SPI Flash Size : 8MB

I (49) boot: Enabling RNG early entropy source...

I (54) boot: Partition Table:

I (58) boot: ## Label            Usage          Type ST Offset   Length

I (65) boot:  0 nvs              WiFi data        01 02 00009000 00006000

I (73) boot:  1 phy_init         RF data          01 01 0000f000 00001000

I (80) boot:  2 factory          factory app      00 00 00010000 00100000

I (88) boot: End of partition table

I (92) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0dc44h ( 56388) map

I (110) esp_image: segment 1: paddr=0001dc6c vaddr=3fc92500 size=023ach (  9132) load

I (113) esp_image: segment 2: paddr=00020020 vaddr=42000020 size=1a66ch (108140) map

I (136) esp_image: segment 3: paddr=0003a694 vaddr=3fc948ac size=00608h (  1544) load

I (137) esp_image: segment 4: paddr=0003aca4 vaddr=40374000 size=0e4b4h ( 58548) load

I (161) boot: Loaded app from partition at offset 0x10000

I (161) boot: Disabling RNG early entropy source...

I (172) cpu_start: Multicore app

I (182) cpu_start: Pro cpu start user code

I (182) cpu_start: cpu freq: 160000000 Hz

I (182) cpu_start: Application information:

I (185) cpu_start: Project name:     async_memcpy

I (190) cpu_start: App version:      d6b7f7a-dirty

I (196) cpu_start: Compile time:     Nov 15 2023 20:47:26

I (202) cpu_start: ELF file SHA256:  7c7112055...

I (207) cpu_start: ESP-IDF:          v5.3-dev-277-gc8243465e4

I (214) cpu_start: Min chip rev:     v0.0

I (218) cpu_start: Max chip rev:     v0.99

I (223) cpu_start: Chip rev:         v0.1

I (228) heap_init: Initializing. RAM available for dynamic allocation:

I (235) heap_init: At 3FC95790 len 00053F80 (335 KiB): RAM

I (241) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM

I (247) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM

I (253) heap_init: At 600FE010 len 00001FD8 (7 KiB): RTCRAM

I (261) spi_flash: detected chip: generic

I (264) spi_flash: flash io: dio

I (269) sleep: Configure to isolate all GPIO pins in sleep state

I (275) sleep: Enable automatic switching of GPIO sleep configuration

I (283) main_task: Started on CPU0

I (293) main_task: Calling app_main()

I (293) async_memcpy:



async_memcpy!



I (293) async_memcpy: Allocating memory for buffers...

I (303) async_memcpy: Initializing source buffer...

I (303) async_memcpy: Installing async_memcpy driver...

D (313) gdma: new group (0) at 0x3fc9b05c

D (313) gdma: new pair (0,0) at 0x3fc9b0e4

D (323) gdma: new tx channel (0,0) at 0x3fc9b024

D (323) gdma: new rx channel (0,0) at 0x3fc9b104

D (333) gdma: tx channel (0,0), (0:32) bytes aligned, burst enabled

D (333) gdma: rx channel (0,0), (0:32) bytes aligned, burst disabled

D (343) gdma: install interrupt service for rx channel (0,0)

I (353) async_memcpy: Creating semaphore...

I (353) async_memcpy: Starting the async_memcpy to transfer 100000 bytes...

E (363) async_mcp: esp_async_memcpy(21): invalid argument

ESP_ERROR_CHECK failed: esp_err_t 0x102 (ESP_ERR_INVALID_ARG) at 0x420084c1

0x420084c1: app_main at D:/Ferret/Dev/esp32/Tests/Async_memcpy/main/main.c:102 (discriminator 1)



file: "./main/main.c" line 102

func: app_main

expression: esp_async_memcpy(driver, _dest, _source, size, my_async_memcpy_cb, semaphore)



abort() was called at PC 0x40379ca7 on core 0

ex40379ca7: _esp_error_check_failed at C:/esp32/esp-idf_master/esp-idf/components/esp_system/esp_err.cN:o50n









Backtrace: 0x403758a6:0x3fc99340 0x40379cb1:0x3fc99360 0x40380441:0x3fc99380 0x40379ca7:0x3fc993f0 0x420084c1:0x3fc99420 0x42019813:0x3fc99460 0x4037a515:0x3fc99490

Waiting for the device to reconnect0x403758a6: panic_abort at C:/esp32/esp-idf_master/esp-idf/components/esp_system/panic.c:472



0x40379cb1: esp_system_abort at C:/esp32/esp-idf_master/esp-idf/components/esp_system/port/esp_system_chip.c:93



0x40380441: abort at C:/esp32/esp-idf_master/esp-idf/components/newlib/abort.c:38



0x40379ca7: _esp_error_check_failed at C:/esp32/esp-idf_master/esp-idf/components/esp_system/esp_err.c:50



0x420084c1: app_main at D:/Ferret/Dev/esp32/Tests/Async_memcpy/main/main.c:102 (discriminator 1)



0x42019813: main_task at C:/esp32/esp-idf_master/esp-idf/components/freertos/app_startup.c:208



0x4037a515: vPortTaskWrapper at C:/esp32/esp-idf_master/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:137











ELF file SHA256: 7c7112055



Rebooting...

ESP-ROM:esp32s3-20210327

Build:Mar 27 2021

rst:0xc (RTC_SW_CPU_RST),boot:0xf (SPI_FAST_FLASH_BOOT)

Saved PC:0x4037581c

0x4037581c: esp_restart_noos at C:/esp32/esp-idf_master/esp-idf/components/esp_system/port/soc/esp32s3/system_internal.c:158

Code: Select all

buf = heap_caps_aligned_alloc(GDMA_PSRAM_BURST,len, MALLOC_CAP_SPIRAM);

Code: Untitled.c Select all

_source = heap_caps_aligned_alloc(64, size, MALLOC_CAP_DMA);

_dest = heap_caps_aligned_alloc(64, size, MALLOC_CAP_DMA);

Code: Untitled.c Select all

    config.sram_trans_align = 64;                       // Only works for IRAM at the moment

    config.psram_trans_align = 64;

Code: Select all

    const uint32_t PSRAM_ALIGN = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
    const uint32_t INTRAM_ALIGN = PSRAM_ALIGN;
    const async_memcpy_config_t cfg {
        .backlog = 8,
        .sram_trans_align = INTRAM_ALIGN,
        .psram_trans_align = PSRAM_ALIGN,
        .flags = 0
    };

Code: Select all

heap_caps_aligned_alloc(PSRAM_ALIGN,...,MALLOC_CAP_SPIRAM);

Code: Select all

#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */

Code: Select all

#include <stdio.h>
#include <inttypes.h>
#include "esp_cpu.h"
#include "esp_heap_caps.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "hal/cache_hal.h"

#include "esp_async_memcpy.h"


static const char TAG[] = "DMADEMO";

static bool dmacpy_cb(async_memcpy_t hdl, async_memcpy_event_t*, void* args) {
    BaseType_t r = pdFALSE;
    xTaskNotifyFromISR((TaskHandle_t)args,0,eNoAction,&r);
    return (r!=pdFALSE);
}


void app_main(void)
{

    const uint32_t LEN = 16384;
    const uint32_t PSRAM_ALIGN = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
    const uint32_t INTRAM_ALIGN = PSRAM_ALIGN;
    const async_memcpy_config_t cfg = {
        .backlog = (LEN+4091)/4092,
        .sram_trans_align = INTRAM_ALIGN,
        .psram_trans_align = PSRAM_ALIGN,
        .flags = 0
    };

    ESP_LOGI(TAG, "Allocating 2x %" PRIu32 "kb in PSRAM, alignment: %" PRIu32 " bytes", LEN/1024, PSRAM_ALIGN);

    void* const mem1 = heap_caps_aligned_alloc(PSRAM_ALIGN, LEN, MALLOC_CAP_SPIRAM);

    if(!mem1) {
        ESP_LOGE(TAG, "Alloc 1 failed");
        return;
    }

    void* const mem2 = heap_caps_aligned_alloc(PSRAM_ALIGN, LEN, MALLOC_CAP_SPIRAM);

    if(!mem2) {
        free(mem1);
        ESP_LOGE(TAG, "Alloc 2 failed");
        return;
    }    

    async_memcpy_t handle;
    esp_err_t r = esp_async_memcpy_install(&cfg,&handle);

    if (r == ESP_OK) {

        TaskHandle_t task = xTaskGetCurrentTaskHandle();

        ESP_LOGI(TAG, "Starting DMA copy.");

        const uint32_t tstart = esp_cpu_get_cycle_count();

        r = esp_async_memcpy(handle,mem1,mem2,LEN,&dmacpy_cb,(void*)task);

        if(r == ESP_OK) {
            if(xTaskNotifyWait(0,0,0,1000/portTICK_PERIOD_MS)) {
                ESP_LOGI(TAG, "DMA CPY EXT->EXT took %" PRIu32 " CPU cycles", esp_cpu_get_cycle_count() - tstart);
            } else {
                ESP_LOGE(TAG, "Timed out waiting for DMA CPY.");
            }
        } else {
            ESP_LOGE(TAG, "Failed to start DMA CPY: %i",r);
        }    

        esp_async_memcpy_uninstall(handle);
    } else {
        ESP_LOGE(TAG, "Failed to install DMA driver: %i",r);
    }

    free(mem2);
    free(mem1);

}

Code: Select all

#
# ESP PSRAM
#
CONFIG_SPIRAM=y

#
# SPI RAM config
#
# CONFIG_SPIRAM_MODE_QUAD is not set
CONFIG_SPIRAM_MODE_OCT=y
# CONFIG_SPIRAM_TYPE_AUTO is not set
CONFIG_SPIRAM_TYPE_ESPPSRAM64=y
CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=y
CONFIG_SPIRAM_CLK_IO=30
CONFIG_SPIRAM_CS_IO=26
# CONFIG_SPIRAM_FETCH_INSTRUCTIONS is not set
# CONFIG_SPIRAM_RODATA is not set
CONFIG_SPIRAM_SPEED_80M=y
# CONFIG_SPIRAM_SPEED_40M is not set
CONFIG_SPIRAM_SPEED=80
CONFIG_SPIRAM_BOOT_INIT=y
# CONFIG_SPIRAM_IGNORE_NOTFOUND is not set
# CONFIG_SPIRAM_USE_MEMMAP is not set
CONFIG_SPIRAM_USE_CAPS_ALLOC=y
# CONFIG_SPIRAM_USE_MALLOC is not set
# CONFIG_SPIRAM_MEMTEST is not set
# CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP is not set
# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set
# CONFIG_SPIRAM_ECC_ENABLE is not set
# end of SPI RAM config
# end of ESP PSRAM

Code: Select all

I (37) boot.esp32s3: Boot SPI Speed : 80MHz
I (42) boot.esp32s3: SPI Mode       : QIO
I (47) boot.esp32s3: SPI Flash Size : 16MB
I (51) boot: Enabling RNG early entropy source...
I (57) boot: Partition Table:
I (60) boot: ## Label            Usage          Type ST Offset   Length
I (68) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (75) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (83) boot:  2 factory          factory app      00 00 00010000 00100000
I (90) boot: End of partition table
I (94) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0b2a4h ( 45732) map
I (110) esp_image: segment 1: paddr=0001b2cc vaddr=3fc92600 size=02ae4h ( 10980) load
I (113) esp_image: segment 2: paddr=0001ddb8 vaddr=40374000 size=02260h (  8800) load
I (121) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1a058h (106584) map
I (144) esp_image: segment 4: paddr=0003a080 vaddr=40376260 size=0c29ch ( 49820) load
I (160) boot: Loaded app from partition at offset 0x10000
I (160) boot: Disabling RNG early entropy source...
I (172) octal_psram: vendor id    : 0x0d (AP)
I (172) octal_psram: dev id       : 0x02 (generation 3)
I (172) octal_psram: density      : 0x03 (64 Mbit)
I (177) octal_psram: good-die     : 0x01 (Pass)
I (182) octal_psram: Latency      : 0x01 (Fixed)
I (188) octal_psram: VCC          : 0x01 (3V)
I (193) octal_psram: SRF          : 0x01 (Fast Refresh)
I (199) octal_psram: BurstType    : 0x01 (Hybrid Wrap)
I (204) octal_psram: BurstLen     : 0x01 (32 Byte)
I (210) octal_psram: Readlatency  : 0x02 (10 cycles@Fixed)
I (216) octal_psram: DriveStrength: 0x00 (1/1)
I (222) esp_psram: Found 8MB PSRAM device
I (226) esp_psram: Speed: 80MHz
I (230) cpu_start: Pro cpu up.
I (233) cpu_start: Starting app cpu, entry point is 0x403754d8

I (0) cpu_start: App cpu up.
I (255) cpu_start: Pro cpu start user code
I (255) cpu_start: cpu freq: 240000000 Hz
I (255) cpu_start: Application information:
I (258) cpu_start: Project name:     test2
I (263) cpu_start: App version:      9c643af-dirty
I (275) cpu_start: ELF file SHA256:  c262dca9b5d25f56...
I (281) cpu_start: ESP-IDF:          v5.1-dev-4124-gbb9200acec-dirty
I (288) cpu_start: Min chip rev:     v0.0
I (292) cpu_start: Max chip rev:     v0.99 
I (297) cpu_start: Chip rev:         v0.2
I (302) heap_init: Initializing. RAM available for dynamic allocation:
I (309) heap_init: At 3FC959C8 len 00053D48 (335 KiB): DRAM
I (315) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (322) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (328) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
I (334) esp_psram: Adding pool of 8192K of PSRAM memory to heap allocator
I (342) spi_flash: detected chip: generic
I (346) spi_flash: flash io: qio
I (351) sleep: Configure to isolate all GPIO pins in sleep state
I (357) sleep: Enable automatic switching of GPIO sleep configuration
I (364) app_start: Starting scheduler on CPU0
I (369) app_start: Starting scheduler on CPU1
I (369) main_task: Started on CPU0
I (379) main_task: Calling app_main()
I (379) DMADEMO: Allocating 2x 16kb in PSRAM, alignment: 32 bytes
I (389) DMADEMO: Starting DMA copy.
I (399) DMADEMO: DMA CPY EXT->EXT took 153634 CPU cycles
I (399) main_task: Returned from app_main()

Code: Untitled.c Select all

_source = heap_caps_aligned_alloc(PSRAM_ALIGN, size, MALLOC_CAP_SPIRAM);

Code: Untitled.c Select all

dest = heap_caps_aligned_alloc(PSRAM_ALIGN, size, MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA);