RISC-V HardFP ABI
Posted: Sat Dec 14, 2024 8:20 pm
I've noticed that function calls with floating point arguments are a little heavier than on RISC-V and ARM32, for the same GCC12.2.0, due to the ABI in use. Here's a trivial example:
RISC-V, F-ABI(not for ESP chips):
ESP32-S3:
With larger functions, the overhead is less of a percentage, but has anyone else ever considered what a HardFP ABI would look like for Xtensa?
On a related note, can Espressif mention if future chips will use Xtensa, or if the future is RISC-V for ESP32s?
Code: Select all
float fmac(float a, float b, float c) {
return a * b + c;
}Code: Select all
fmac(float, float, float):
fmadd.s fa0,fa0,fa1,fa2 #do the multiply-accumulate
ret
ESP32-S3:
Code: Select all
fmac(float, float, float):
entry sp, 32
wfr f1, a2 #copy integer reg to FPU reg
wfr f0, a4 #copy integer reg to FPU reg
wfr f2, a3 #copy integer reg to FPU reg
madd.s f0, f1, f2 #do the multiply-accumulate
rfr a2, f0 #copy FPU reg to integer reg
retw.n
On a related note, can Espressif mention if future chips will use Xtensa, or if the future is RISC-V for ESP32s?