I2S clock freq precision/stability?
Posted: Mon Mar 03, 2025 8:29 am
Running an ESP32-S3 with I2S PDM @48kHz sample rate, the CLK output should be 6.144 MHz, but measuring with an oscilloscope, it is closer to 6.17 Mhz which is a discrepancy of almost 0.5% (!!!)
Is this to be expected? Using the default clock initializer macros:
Is this to be expected? Using the default clock initializer macros:
Code: Select all
/* Step 2: Setting the configurations of PDM TX mode and initialize the TX
* channel The slot configuration and clock configuration can be generated
* by the macros These two helper macros is defined in 'i2s_pdm.h' which can
* only be used in PDM TX mode. They can help to specify the slot and clock
* configurations for initialization or re-configuring */
i2s_pdm_tx_config_t pdm_tx_cfg = {
.clk_cfg = I2S_PDM_TX_CLK_DAC_DEFAULT_CONFIG(sample_rate),
/* The data bit-width of PDM mode is fixed to 16 */
.slot_cfg = I2S_PDM_TX_SLOT_DEFAULT_CONFIG(
I2S_DATA_BIT_WIDTH_16BIT,
(stereo ? I2S_SLOT_MODE_STEREO : I2S_SLOT_MODE_MONO)),
.gpio_cfg =
{
.clk = PDM_TX_CLK_IO,
.dout = PDM_TX_DOUT_IO,
.invert_flags =
{
.clk_inv = false,
},
},
};
pdm_tx_cfg.slot_cfg.hp_en = false;
ESP_ERROR_CHECK(i2s_channel_init_pdm_tx_mode(tx_chan, &pdm_tx_cfg));