ESP32 Forum

Posted: **Fri Apr 25, 2025 6:22 pm**

Hello. I'm trying to send a 24MHz clock signal on the 1st pin of an esp32 wroom 32 MCU using LEDC driver. However, I get this weird result

: Screenshot 2025-04-25 205447.png (11.93 KiB) Viewed 85 times

. I tried playing around with clock sources and frequency and got it to work at 1000Hz, 10MHz and 20MHz. 1000Hz was working as intended while 10Mhz and 20Mhz with APB_CLK produced less than specified, 4 and 8MHz respectively. Another thing to mention is that in instances where it worked, e.g. 1000Hz, the same unintelligible pattern shown above could be seen briefly after resetting the esp32 (it stabilized after a while).

Something else that caught my eye is that in cases where it produced the intended result, e.g. 1000Hz, I could still observe some irregularities in the wave pattern, for example the duty cycle shifting to about 67% for a short period of time. I can easily see this as just being a shortcoming of the hardware, but I thought I'd still mention it...

Here's the code:

Code: Select all

extern "C" void app_main(void)
{
    gpio_set_direction(MCLK_PIN, GPIO_MODE_OUTPUT);

    ledc_timer_config_t timer_cfg = {
        .speed_mode = LEDC_HIGH_SPEED_MODE,
        .duty_resolution = LEDC_TIMER_1_BIT,
        .timer_num = LEDC_TIMER_0,
        .freq_hz = 24000000,
        .clk_cfg = LEDC_USE_APB_CLK
    };
    ESP_ERROR_CHECK(ledc_timer_config(&timer_cfg));

    ledc_channel_config_t chan_cfg = {
        .gpio_num = MCLK_PIN,
        .speed_mode = LEDC_HIGH_SPEED_MODE,
        .channel = LEDC_CHANNEL_0,
        .intr_type = LEDC_INTR_DISABLE,
        .timer_sel = LEDC_TIMER_0,
        .duty = 1,
        .hpoint = 0,
        .sleep_mode = LEDC_SLEEP_MODE_NO_ALIVE_NO_PD
    };
    ESP_ERROR_CHECK(ledc_channel_config(&chan_cfg));

    while (true) {
        vTaskDelay(pdMS_TO_TICKS(10));
    }
}

By the way, I made sure that power management and dynamic frequency are disabled.
SDKCONFIG: https://pastebin.com/HE0FsgZ3

I'm new to esp32 development so I might've missed something obvious

. Appreciate any help! P.S sorry for bad english..

Posted: **Sun Apr 27, 2025 7:21 am**

Is the sampling rate of your logic analyzer enough to sample the clock? At 50% duty cycle, the sampling rate of the LA should be at least 2x the output frequency; more if the duty cycle is not 50%.

Posted: **Sun Apr 27, 2025 5:49 pm**

OMG I feel so dumb... My LA IS rated for 24MHz

. I can't believe I didn't realize it earlier! Thank you!

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