ESP32 GPIO drive strength
Posted: Tue Jun 10, 2025 1:12 pm
Based on some posts here (e.g. viewtopic.php?f=2&t=2027), I expected that the GPIO drive strength current limits should adjust the GPIO output impedance, which could be used to optimize signal/noise on digital IO lines. To confirm this, I measured the output impedance by hooking an ESP32 up to a 75 ohm coax cable and fast oscilloscope. I then recorded the rise time and reflection coefficient and backed out the source impedance.
Surprisingly the rise time (16 ns) and source impedance (30 ohms) are constant for all settings of drive strength, at least on my ESP-WROOM-32 development board. I used ESPHome as an easy way to test since it exposes this setting for its GPIO. Looking at the source code, gpio_set_drive_capability which I think looks ok so I don't think this is an ESPHome issue.
Before I spend a lot more time testing more, what is the "drive strength" setting expected to do? Is it just a current limiter that kicks in after a delay or does it actually parallel more output stage drivers to supply more current? The documentation says it sets the "drive capability of the pad", which certainly sounds like it should have some measurable effect.
Surprisingly the rise time (16 ns) and source impedance (30 ohms) are constant for all settings of drive strength, at least on my ESP-WROOM-32 development board. I used ESPHome as an easy way to test since it exposes this setting for its GPIO. Looking at the source code, gpio_set_drive_capability which I think looks ok so I don't think this is an ESPHome issue.
Before I spend a lot more time testing more, what is the "drive strength" setting expected to do? Is it just a current limiter that kicks in after a delay or does it actually parallel more output stage drivers to supply more current? The documentation says it sets the "drive capability of the pad", which certainly sounds like it should have some measurable effect.