ESP32 Forum

We are using a custom ESP32 board connected to a CC2652R7 over UART. Programming is done via an external USB-to-UART module with connections to TX, RX, GND, RESET (EN), and VCC. The programmer is disconnected after uploading.

However, we’ve observed that occasionally after powering on, the ESP32 boots into Download Mode (UART). The log shows:

rst:0x1 (POWERON_RESET), boot:0x1 (DOWNLOAD_BOOT(UART0/UART1/SDIO_FEI_REO_V2))

Key details:

IO14 and IO27 are used in the design.

This issue occurs rarely, approximately 1 out of every 10 power-ons.

Sometimes it occurs even after we remove EN and GPIO0 wiring and keep only TX, RX, and GND.

We verified that GPIO0 is not pulled low intentionally.

Reset circuitry appears to be stable during boot.


We’d appreciate any insights on:

What could cause this intermittent entry into download mode?

Any recommended pull-up/down configuration or debounce suggestions for EN and GPIO0?

It seems is a bad design, i myself has never left one pin open in that way, nor for atmega, nrf, st or esp.

I recommend always checking a dev board to learn from it before indulging into design, here is an example https://dl.espressif.com/dl/schematics/ ... 00812A.pdf

You can do a few things. Use a 0u1 capacitor like the one in that schematic against ground, or a 10k resistor against 3V3

Hi, thanks for checking out my post. I’ve shared my ESP32 design for review—could you please verify if everything looks correct? Also, let me know if you notice anything that might need improvement or could cause issues in functionality or performance. Your feedback will help me refine the design.

Remove C33.

Hi thanks for that but c33 already removed can you give any suggestions other than that

Hm. You do still have R9 and C24 in place?