ESP32 Forum

• Allow images to be captured around 15FPS at maximum resolution (2592x1944), you can also achieve 20FPS QHD/FHD with this setting enabled.

• Allow images to be captured around 20FPS at maximum resolution (2048x1536), you can also achieve 30FPS FHD with this setting enabled.

• Rewrite esp_cam_io_parl headers and C code (Using esp_driver_parlio currently has some limitations). [Not Complete]

• Merge and rewrite esp_camera_sensor into esp_cam_io_parl. [Pending]

• ETM support for some DVP signals (trigger PARLIO RX start). [Not Complete]

• Allow methods to replicate the valid signal for targets that doesn't have sufficient bit width. [Not Complete]

Hey, we are looking to connect our ov5640 camera to esp32 c5 dev board. I dont have much hardware experience. If you could help me out on how you managed to connect them wopuld be of great help! Thanks

I actually was able to get the pin mapping and connected the relevant pins and tested the

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Simple Camera Capture

code and got successful image capture logs, though when I tried again after some time, I now am only getting capture failed due to timeout errors. Do you know what could be going wrong here?

Thanks for providing the camera example.

Just as an additional note: there appears to be a bug in the SDK related to the sampling edge.

In the camera example, config->pclk_sample_edge is never initialized, so it effectively defaults to PARLIO_SAMPLE_EDGE_NEG (0). As a result, parlio_rx_soft_delimiter_config_t.sample_edge is also set to NEG, yet the code still works.

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        parlio_rx_soft_delimiter_config_t rx_delimiter_config = {
            .sample_edge = config->pclk_sample_edge,
            .eof_data_len = esp_cam_io_parl->payload_size,
            .timeout_ticks = 0,
        };

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  typedef enum {
    PARLIO_SAMPLE_EDGE_NEG, /*!< Sample data on falling edge of clock */
    PARLIO_SAMPLE_EDGE_POS, /*!< Sample data on rising edge of clock */
} parlio_sample_edge_t;

Here is the first HREF after VSYNC. The bytes ff f8 (low bits → f and 8) should definitely be sampled on the rising edge:
ffd8.png

In C6 driver code comments are broken: https://github.com/espressif/esp-idf/bl ... ruct.h#L72

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        /** rx_clk_edge_sel : R/W; bitpos: [26]; default: 0;
         *  Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable
         *  sampling data on the falling edge of rx clock.
         */

I can not find register definition for esp32c5, but for esp32c6, O in PARL_IO_RX_LEVEL_SUBMODE_SEL means Rising Edge.

.pclk_sample_edge 

Does anyone know the correct way to calculate PCLK frequency and FPS from the OV5640 configuration parameters?

I am trying to verify whether the VCO, SYSCLK, and PCLK frequencies are within valid ranges when using a 24 MHz XCLK.

I am implementing a calculator:
https://romanlut.github.io/hx-esp32-cam ... lator.html

I followed the formulas used in the esp32-camera driver:
https://github.com/espressif/esp32-came ... 640.c#L200

However, the calculated values do not match the actual measured behavior.