P4-JIT: Dynamic Code Loading for ESP32-P4 (2-Second Development Cycles)
Posted: Sat Dec 27, 2025 11:57 pm
I built a JIT compilation system for ESP32-P4 that eliminates firmware reflashing during development.
PROBLEM IT SOLVES:
Traditional ESP32 workflow: Write code → Compile → Flash → Test = 30-60 seconds
P4-JIT workflow: Write code → Upload → Test = 2-3 seconds
KEY FEATURES:
- Native RISC-V execution (no interpreter overhead)
- Tests ESP32-P4 PIE SIMD instructions on real hardware
- Python + NumPy interface
- Automatic memory management
- Call firmware functions (printf, malloc, etc.)
USE CASES:
- ML/DSP algorithm prototyping
- Neural network kernel optimization
- Real-time audio processing development
LINKS:
Demo video: https://youtu.be/s5sUW7lRV1E
GitHub: https://github.com/BoumedineBillal/esp32-p4-jit
Documentation: Complete with Jupyter notebook tutorials
Built for my Master's thesis. Open to feedback and collaboration!
PROBLEM IT SOLVES:
Traditional ESP32 workflow: Write code → Compile → Flash → Test = 30-60 seconds
P4-JIT workflow: Write code → Upload → Test = 2-3 seconds
KEY FEATURES:
- Native RISC-V execution (no interpreter overhead)
- Tests ESP32-P4 PIE SIMD instructions on real hardware
- Python + NumPy interface
- Automatic memory management
- Call firmware functions (printf, malloc, etc.)
USE CASES:
- ML/DSP algorithm prototyping
- Neural network kernel optimization
- Real-time audio processing development
LINKS:
Demo video: https://youtu.be/s5sUW7lRV1E
GitHub: https://github.com/BoumedineBillal/esp32-p4-jit
Documentation: Complete with Jupyter notebook tutorials
Built for my Master's thesis. Open to feedback and collaboration!