ESP32-P4: What's the maximum QSPI frequency through GPIO Matrix?
Posted: Mon Mar 23, 2026 8:49 am
The ESP-IDF documentation for the SPI slave driver on the P4 (https://docs.espressif.com/projects/esp ... slave.html) states:
The documentation for the SPI master driver (https://docs.espressif.com/projects/esp ... aster.html) on the other hand states:When an SPI Host is set to 80 MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same compared to routing them via IO_MUX.
And then in another section it saysWhen an SPI Host is set to 40 MHz or lower frequencies, routing SPI pins via the GPIO matrix will behave the same compared to routing them via IOMUX.
So, what is correct? What frequency can be supported (in particular in QSPI) through GPIO Matrix? 26Mhz, 40Mhz or 80Mhz?On ESP32, due to the delay of GPIO matrix, the maximum frequency SPI Master can correctly samples the slave's output is lower than the case using IOMUX. Typical maximum frequency communicating with an ideal slave without data output delay: 80MHz (IOMUX pins) and 26MHz (GPIO matrix pins)