LP CPU errors and warning while starting debug session (Espressive IDE)
Posted: Sun May 03, 2026 8:42 am
Hello everyone,
when I start a debug session with the Espressive IDE, I see errors and warning from the Low Power CPU. How can I disable the debugging of the LP CPU?
Error: [esp32c6.lp.cpu] Timed out after 5s waiting for busy to go low (abstractcs=0x10001002). Increase the timeout with riscv set_command_timeout_sec.
Error: [esp32c6.lp.cpu] Timed out after 5s waiting for busy to go low (abstractcs=0x10001102). Increase the timeout with riscv set_command_timeout_sec.
Error: [esp32c6.lp.cpu] Unexpected read of fp via program buffer.
Warn : [esp32c6.lp.cpu] Register csr_ustatus does not exist, which is part of an SMP group where this register does exist.
...
Error: esp32c6.lp.cpu: Failed to get flash bank (-4)!
Error: [esp32c6.lp.cpu] can't add breakpoint: unknown reason
Thanks
Nikolai
when I start a debug session with the Espressive IDE, I see errors and warning from the Low Power CPU. How can I disable the debugging of the LP CPU?
Error: [esp32c6.lp.cpu] Timed out after 5s waiting for busy to go low (abstractcs=0x10001002). Increase the timeout with riscv set_command_timeout_sec.
Error: [esp32c6.lp.cpu] Timed out after 5s waiting for busy to go low (abstractcs=0x10001102). Increase the timeout with riscv set_command_timeout_sec.
Error: [esp32c6.lp.cpu] Unexpected read of fp via program buffer.
Warn : [esp32c6.lp.cpu] Register csr_ustatus does not exist, which is part of an SMP group where this register does exist.
...
Error: esp32c6.lp.cpu: Failed to get flash bank (-4)!
Error: [esp32c6.lp.cpu] can't add breakpoint: unknown reason
Thanks
Nikolai