ESP32 Forum

There is some inconsistency in the ESP32-S31 Series Datasheet Pre-release v0.2 document. I know it's very early, but I was wondering are there TWO HP cores and one LP core, or is the "dual core" of the S31 more like BIG.little in ARM with one HP and one LP core? The document implies two HP cores in some cases, and one HP core in other cases.

Two HP cores plus one LP core. For HP cores, only HP core 1 with SIMD (xespv).

How will that be managed with the scheduler? If you use SIMD, will it pin to core1?

Yes, any invalid PIE use will trigger illegal instruction exception. In panic_handler, the task will be pinned to core 1 automatically.