ESP32 Forum

Hi,

The C6 TRM states SCL in master mode should not exceed 400 kHz. My setup runs at 1 MHz without obvious issues and I want to understand the reliability implications.

My setup is as follows:
- SparkFun Qwiic Pocket Dev Board (ESP32-C6)
- ICM-45xxx IMU
- 1 MHz I2C clock, short Qwiic 5 cm cable, 2.2 kOhm pull-ups
- Reads are consistent, and no bus errors have been reported after several hours of testing under normal conditions.

A 2017 thread (viewtopic.php?t=3150) showed that 1 MHz worked on the original ESP32, and 20 mA was cited as a sufficient drive strength for FM+. Nothing C6-specific was found.

1. Is the 400 kHz limit a hard silicon constraint, or does it hold under good electrical conditions, such as a short bus, low capacitance, and strong pull-ups?
2. Are there any known failure modes above 400 kHz for the C6? For example, is there data corruption due to temperature, supply noise, or long runtime?
3. Are there any C6-specific errata or IDF driver issues above 400 kHz, such as clock stretching, arbitration, or interrupt latency?
4. Has anyone deployed the ESP32-C6 at 1 MHz for an extended period of time and experienced any degradation?

The main concern is reliability over time and under different conditions.

Thanks

It's probably because we didn't bother to test anything above 400kHz. It probably works fine; the silicon itself isn't really that constrained; if you get any issues it may be because of (analog) setup/hold time violations, or if you go really high in speeds (10s of MHz) you might run into the limit of whatever clock is used to sample the signals. Do take care with that if you ever want to use DFS for power saving as it may lower the clock rate to the I2C peripheral to something unusable at those out-of-spec high speeds. Note that we technically reserve the right to change undocumented behaviour in future chip revisions, so while it may work today it may not work tomorrow, but honestly given the nature of the thing I think that's a very low risk.