I think the early
watchdog activation strategy makes sense from a system reliability perspective. While moving watchdog configuration into the bootloader provides more software flexibility, enabling the basic protection already at hardware/BootROM level avoids a critical window where the device could become permanently stuck before the bootloader gains control. For a modern SoC like the ESP32-S31, early recovery capability seems like a reasonable design choice.
4.1.4.9 Watchdog Timers (WDT)
ESP32-S31 contains three digital watchdog timers: one in each of the two timer groups (called Main System
Watchdog Timers, or MWDT) and one in the LP system (called the RTC Watchdog Timer, or RWDT).
In SPI Boot mode, RWDT and the MWDT in timer group 0 are enabled automatically in order to detect errors that
may occur during the flash boot process and facilitate recovery.
ESP32-S31 also has one analog watchdog timer: Super watchdog (SWD). It is an ultra-low-power circuit in
analog domain that helps to prevent the system from operating in a sub-optimal state and resets the system if
required.
Feature List
• Four stages, each with a separately programmable timeout value and timeout action
• Timeout actions:
– MWDT: interrupt, HP CPU reset, HP core reset
– RWDT: interrupt, HP CPU reset, HP core reset, system reset
• Flash boot protection under SPI Boot mode at stage 0:
– MWDT0: HP core reset upon timeout
– RWDT: system reset upon timeout
• Write protection that makes WDT register read only unless unlocked
• 32-bit timeout counter
• Clock source:
– MWDT: PLL_F80M_CLK, RC_FAST_CLK or XTAL_CLK
– RWDT: LP_DYN_SLOW_CLK
