[Showcase] S-OS V-RAM Engine for ESP32: Paging 8MB Virtual Memory with 43.5x Compression (No PSRAM Required)
Posted: Fri Aug 07, 2026 12:56 am
Hi Espressif Community & Engineers!
I wanted to share a dynamic C++ Virtual Memory Engine (V-RAM) I’ve designed, implemented, and stress-tested specifically for standard ESP32 boards without requiring hardware PSRAM.
Problem Statement
When scaling TinyML models, AI neural lattices, display framebuffers, or local databases, standard ESP32 WROOM chips quickly hit the ~320KB SRAM wall. Adding hardware PSRAM (WROVER/S3-N8R8) increases BOM costs, power consumption, and PCB layout complexity.
Architecture Overview
S-OS V-RAM Engine provides a flat 32-bit linear address space over SPI NOR Flash (LittleFS) using an in-flight context-adaptive RangeCoder + LZ77 compression pipeline:
• Pimpl Pattern: Opaque C++ pointer interface hiding internal RangeCoder state models and LZ77 hash tables.
• In-Flight Compression: RAM blocks are compressed before LRU eviction to Flash storage.
• FreeRTOS Dual-Core Thread Safety: Recursive mutexes for safe concurrent access across tasks (e.g. reflex loops on Core 0, strategic V-RAM access on Core 1).
• C++ Template API: Simple vram.put<T>(address, val) and vram.get<T>(address) methods over a flat 32-bit address space.
Empirically Proven Benchmarks (8.0 MB Stress Test on ESP32-WROOM):
• Virtual Address Capacity: 8,388,608 Bytes (8.0 MB) tested.
• Actual Compressed Flash Usage: 192,647 Bytes (~192 KB).
• Real-World Payload Compression: Up to 43.54x (Peak) / 3x–8x on real telemetry & neural weights.
• Data Integrity: 100% Perfect (0 Errors) across 8.38M bytes & 1,000 random thrashing page fault swaps.
• Sequential Write Speed: Up to 117.86 KB/s.
• Sequential Read Speed: Up to 86.26 KB/s.
• Static Memory Footprint: Minimal (~1.9 KB).
Page Fault Latency Breakdown (PHASE 3):
During a worst-case page thrashing benchmark (1,000 random page faults across 8MB with a 128KB cache pool):
• Page Swap Latency (Flash Miss): ~970 ms (Includes 16KB compress, LittleFS NOR Flash 4KB sector erase/write, flash read, and RangeCoder decompression).
• In-RAM Cache Hit Latency: < 0.001 ms (sub-microsecond).
The Community Edition (capped at 512KB V-RAM for evaluation and non-commercial projects) is available on GitHub.
GitHub Repository: https://github.com/StepanoskiZ/vram-engine-esp32
Technical Specs & Commercial Licensing: https://zoranstepanoski-prof-website.fly.dev/
I would love to hear feedback from Espressif engineers and the community!
I wanted to share a dynamic C++ Virtual Memory Engine (V-RAM) I’ve designed, implemented, and stress-tested specifically for standard ESP32 boards without requiring hardware PSRAM.
Problem StatementWhen scaling TinyML models, AI neural lattices, display framebuffers, or local databases, standard ESP32 WROOM chips quickly hit the ~320KB SRAM wall. Adding hardware PSRAM (WROVER/S3-N8R8) increases BOM costs, power consumption, and PCB layout complexity.
Architecture OverviewS-OS V-RAM Engine provides a flat 32-bit linear address space over SPI NOR Flash (LittleFS) using an in-flight context-adaptive RangeCoder + LZ77 compression pipeline:
• Pimpl Pattern: Opaque C++ pointer interface hiding internal RangeCoder state models and LZ77 hash tables.
• In-Flight Compression: RAM blocks are compressed before LRU eviction to Flash storage.
• FreeRTOS Dual-Core Thread Safety: Recursive mutexes for safe concurrent access across tasks (e.g. reflex loops on Core 0, strategic V-RAM access on Core 1).
• C++ Template API: Simple vram.put<T>(address, val) and vram.get<T>(address) methods over a flat 32-bit address space.
Empirically Proven Benchmarks (8.0 MB Stress Test on ESP32-WROOM):• Virtual Address Capacity: 8,388,608 Bytes (8.0 MB) tested.
• Actual Compressed Flash Usage: 192,647 Bytes (~192 KB).
• Real-World Payload Compression: Up to 43.54x (Peak) / 3x–8x on real telemetry & neural weights.
• Data Integrity: 100% Perfect (0 Errors) across 8.38M bytes & 1,000 random thrashing page fault swaps.
• Sequential Write Speed: Up to 117.86 KB/s.
• Sequential Read Speed: Up to 86.26 KB/s.
• Static Memory Footprint: Minimal (~1.9 KB).
Page Fault Latency Breakdown (PHASE 3):During a worst-case page thrashing benchmark (1,000 random page faults across 8MB with a 128KB cache pool):
• Page Swap Latency (Flash Miss): ~970 ms (Includes 16KB compress, LittleFS NOR Flash 4KB sector erase/write, flash read, and RangeCoder decompression).
• In-RAM Cache Hit Latency: < 0.001 ms (sub-microsecond).
The Community Edition (capped at 512KB V-RAM for evaluation and non-commercial projects) is available on GitHub.
GitHub Repository: https://github.com/StepanoskiZ/vram-engine-esp32
Technical Specs & Commercial Licensing: https://zoranstepanoski-prof-website.fly.dev/I would love to hear feedback from Espressif engineers and the community!