Thanks, that's much clearer now.

The WROOM module datasheet has a Pin Description table at page 13 which mentions LP UART and UART0, but not UART1.

I need to use RS485 with ESP32-C5-WROOM module. Is UART1 accessible for the WROOM module?

I'm using a custom board with flash 25SF321B and esp32-s3. The chip cannot detect the flash, here's the log:

Rebooting...
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0xb (SPI_FAST_FLASH_BOOT)
Saved PC:0x40375de1
SPIWP:0xee
mode:DIO, clock div:1
load:0x3fce3810,len ...

Finally I found the reason - I was doing memcpy to a string literal. This gave no warnings (and also somehow worked). When the code was fixed, esp_ota_end does not fail.

It appears that a call to esp_partition_get_sha256 also results in the same crash.

I added the following code (taken from native OTA example):

uint8_t sha_256[HASH_LEN] = {0};
esp_partition_t partition;

// get sha256 digest for the partition table
partition.address = ESP_PARTITION_TABLE ...

Hello,

Unfortunately I cannot share my complete application.

I've enabled Debug log level, boot log attached.

What I also did was comment out the while loop in the panic handler:
// For cache error, pause the non-offending core - offending core handles panic
if (panic_get_cause(frame) == PANIC ...

After another day of fruitless bug hunting, I am considering the possibility of cache error. I've disabled the TWAI driver, and deregistered the FreeRTOS tick hook just before calling esp_ota_end - with no effect.

Edit: I also checked all running tasks' stack before calling esp_ota_end, did not ...

Another lead: the code execution ends in panic_handlers.c :

// For cache error, pause the non-offending core - offending core handles panic
if (panic_get_cause(frame) == PANIC_RSN_CACHEERR && core_id != esp_cache_err_get_cpuid()) {
// Only print the backtrace for the offending core in case of ...

Updating the topic again in the hope that anyone with a similar problem will shed some light.

The reset reason which is printed out after the chip reboots is rst:0x8 (TG1WDT_SYS_RST),boot:0xb (SPI_FAST_FLASH_BOOT)
It is defined in rtc.h as " Timer Group1 Watch dog reset digital core" . Looking in ...