Yeah sounds plausible, and other manufacturers do this as well. I just find it a bit silly that Espressif creates an embellished announcement with all superlatives and marketing hype terms each time. Intel and AMD also make CPU's on demand, I don't think they do the "announcements" like this.

Just ...

I always though the same, but apparently it's otherwise.

Hi,

Thanks for your comments!

So for the moment I am seeing the S31 as an "intermediate" model to the real serious showstopper then.

I am really surprised of the amount of models Espressif has introduced over the last two years. Some of them are almost exactly the same of another model, but ...

Just very sparsely technical specifications available, mostly marketing speak...

What do we actually know?

It looks like a ESP32-S3 but
- the two Xtensa cores are replaced by RISC-V cores (which was to be expected)
- classic Bluetooth (re-)added
- gigabit PHY added
- MCPWM removed?
- Thread/Zigbee ...

AFAIK clock stretching is supported. But it's a discouraged practice.

Interesting, thanks!

I am already, eagerly following any progress/announcements around the P4, indeed. And yes, I do need wlan and bluetooth, so for now it's a no-go.

I don't need I2C slave access, so that's no problem. So as long as all of them can be accessed the same way, I'd be happy. Even if ...

I am not so familiar with RISC-V, doesn't it have register windows? Or is not (yet) enabled in the ESP's?

Back on topic:

I'd like to see an ESP32-S3 (so with all the bells and thrills possible) but then with 2 RISC-V cpu's, high speed of course, 240 MHz minimum. As discussed before three or even ...

Are you discussing RISC-V now? As Xtensa has a register window?

Yeah more wishes from me:
- three or even just two I2C modules that have exactly the same features and the same interface, even though one of them is part of the RTC/ULP module. Now the RTC/ULP is very different and is very limited.
- I2C hardware modules with less bugs/workarounds required

The ESP-S3 is based on Xtensa cores which, as opposed to the ESP8266's version, have a register window. In many cases no access to the stack is required, only the register window start pointer is moved.

I do not know if the RISC-V cores also have this feature, but most modern processors have this ...