If anyone is reading this in the future:

- Olimex's popular design is awful and totally incorrect. It had way too much delay (around 500ms if I remember off the top of my head), and did not start the crystal fast enough, so code had to be added to ESP-IDF SDK (happens when the board type is set to ...

Thank you, Sprite. I saw that table but the paragraph above it confuses me.

I think this paragraph should be rewritten to be clearer:

" At system reset, the latches sample the bit values of their respective strapping pins"

It makes it sound like all soft resets (like OTA Updates, "esp_restart ...

The ESP32 can receive clock signal on GPIO 0 to sync with external Ethernet PHYs.

But as most people know, the clock signal interferes with the ESP32 bootstrap pin (GPIO 0 chooses between regular/firmware flashing boot modes).

Therefore, it's necessary to delay the clock signal startup to happen ...

I use a ESP32-WROOM-32E:

https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32e_esp32-wroom-32ue_datasheet_en.pdf

The datasheet says:

All strapping pins have latches. At system reset, the latches sample the bit values of their respective strapping
pins and store them until ...

I registered just to add:

You most likely just encountered the unfixable hardware bug in the ESP32, which was discovered in late 2024:

https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/clock-rmii-clock-when-using-ethernet-and-wifi.html

In short:

The ...