Search found 8 matches

by xiaoxufeng
Mon Feb 11, 2019 3:39 pm
Forum: ESP32 IDF
Topic: ESP32 spi_device_queue_trans error
Replies: 2
Views: 95

Re: ESP32 spi_device_queue_trans error

tatulea wrote:
Fri Feb 08, 2019 10:50 am
It looks like the problem was from DMA. I set it to 0 and I had to put it to 1 in order to use DMA in transaction.
Hi tatulea,
Thanks for your sharing of the debug result.
We will add a check in the code to help you detect this in the future.
by xiaoxufeng
Fri Aug 31, 2018 5:21 am
Forum: ESP32 IDF
Topic: SDIO Slave. Sending bug.
Replies: 3
Views: 560

Re: SDIO Slave. Sending bug.

Hi alexey, I think this doesn't make sure all your transactions are done: while(ESP_ERR_TIMEOUT == sdio_slave_send_get_finished(&tst, 0)){}; The driver needs you to keep the buffer until the sending is finished, so you have to check every one of them is finished or not. 1. To check whether is caused...
by xiaoxufeng
Tue Aug 21, 2018 7:38 am
Forum: ESP32 IDF
Topic: SDIO slave. How to change timings?
Replies: 4
Views: 622

Re: SDIO slave. How to change timings?

Hi Alexy, I've just tested on my board again and found no problem: the slave data output right in 10-12.5ns after the launch edge set (posedge if PSEND and negedge if NSEND) at 400KHz. Your problem may be: the hold time requirement is not meet on either side: host->slave side, I saw esp32 host outpu...
by xiaoxufeng
Mon Aug 20, 2018 9:21 am
Forum: ESP32 IDF
Topic: SDIO slave. How to change timings?
Replies: 4
Views: 622

Re: SDIO slave. How to change timings?

Hi Alexy, One more thing, the delay from CLK posedge to data stable time is about 12.5ns from my test (PSEND), which is over half a clock of 50MHz (HS mode). This is possibly why you think the data is given at negedge. You can try again in DS mode or even slower. The protocol allows 14ns after the p...
by xiaoxufeng
Mon Aug 20, 2018 7:56 am
Forum: ESP32 IDF
Topic: SDIO slave. How to change timings?
Replies: 4
Views: 622

Re: SDIO slave. How to change timings?

Hello Alexy, 1. Firstly, yes, you are right, the SD protocol requires timing of: DS mode: launch: negtive edge, latch: postive edge HS mode: launch: postive edge, latch: postive edge If your esp32 launches data at HS mode, it's obviously wrong. BTW, our host cannot launch data at negtive edge now, a...
by xiaoxufeng
Tue May 22, 2018 8:29 am
Forum: ESP32 IDF
Topic: Default state of MOSI
Replies: 2
Views: 401

Re: Default state of MOSI

Agree to kolban. Some additions, ESP32 peripheral seems to keep the MOSI output of the last sent bit. If you really cares about the MOSI state when spi is inactive (CS high), please use some tricks to make sure the last bit is 1. e.g. send 1 or 8 more ``0`` bits each transaction, or add a new device...
by xiaoxufeng
Tue May 22, 2018 8:16 am
Forum: ESP32 IDF
Topic: ESP32-WROVER-KIT use of SPI master
Replies: 3
Views: 1163

Re: ESP32-WROVER-KIT use of SPI master

Hi valentin, For the speed (500kHz) you used to test, there's no timing issue at all if all the configurations are right. So please don't care about ``no_delay`` and ``dummy`` too much. Set ``no_delay=0`` and ``dummy=0`` it should work. The maximum frequency is highly related to the slave (MISO dela...
by xiaoxufeng
Mon Aug 28, 2017 10:53 am
Forum: ESP32 IDF
Topic: [SPI master] only recieving first byte from slave
Replies: 1
Views: 1392

Re: [SPI master] only recieving first byte from slave

We've fixed several issues in past days. These issues exist when you use the RX DMA. Please update to the latest idf and have a try. However, I'm afraid there's still something wrong with the half-duplex mode and cannot be fixed in a short time. The issue occurs when DMA is enabled in half-duplex mo...

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