Search found 3 matches
- Wed Mar 04, 2026 6:45 pm
- Forum: Hardware
- Topic: Availability of Xtensa core extensions in ESP32-S3
- Replies: 7
- Views: 564
Re: Availability of Xtensa core extensions in ESP32-S3
If so I would suggest correcting the Table 1.5-1 of the ESP32-s3 TRM. The BR registers are not listed here which is confusing.
- Wed Feb 25, 2026 8:20 pm
- Forum: Hardware
- Topic: Availability of Xtensa core extensions in ESP32-S3
- Replies: 7
- Views: 564
Re: Availability of Xtensa core extensions in ESP32-S3
Sorry to restart an old thread. Does this mean that:
1. For the xtensa lx7 instruction set the boolean instructions like OLT.S, BT, BF, etc. are unavailable for the ESP32-S3. If so can you provide example code for the feature set that replaces this functionality?
2. You state that each core has ...
1. For the xtensa lx7 instruction set the boolean instructions like OLT.S, BT, BF, etc. are unavailable for the ESP32-S3. If so can you provide example code for the feature set that replaces this functionality?
2. You state that each core has ...
- Fri Feb 20, 2026 10:21 am
- Forum: General Discussion
- Topic: FFT - iFFT
- Replies: 6
- Views: 6738
Re: FFT - iFFT
Sorry for restarting an old thread. I am aware we can do:
IFFT(data) = 1/N * conj(FFT(conj(data)))
However for efficiency a dedicated IFFT function would be better. Looking at the math the difference other than the 1/N scaling factor is as "simple" as a sign flip for the exponent of "e" from ...
IFFT(data) = 1/N * conj(FFT(conj(data)))
However for efficiency a dedicated IFFT function would be better. Looking at the math the difference other than the 1/N scaling factor is as "simple" as a sign flip for the exponent of "e" from ...