What would you like to see in The Next Chip?

[dmitrij999]

I'd like ESP32 series to see external DRAM DMA-capable memory controller to be able to provide a smooth framerate on displays

[expresspotato]

We really have no upgrade path with Espressif today...

I hate to admit it, but I agree. They upgrade one thing and remove another. It's slowly been turning into a Hodgepodge of micros.
The P4 had the best shot at having everything until they removed the WiFi.

I say just throw it all in one chip and stop with all these other iterations. It has to be a nightmare for the hardware, software, and documentation guys at espressif to keep up with all these changes.

Yeah I really don't know why they did it. I like Espressif, I think their software stack is incredibly well thought out, cohesive, interoperable and well loved.

Anyone on here actually asked for the P4?

[Writer]

This has a great advantage of backwards compatibility with the IDF for ESP32, so that the developers can easily reuse existing code with the new chip.

[eriksl]

I probably said this before

A chip based on the "new" ARM processor cores but with all of the features of the S3. Just pack everything in what's available, even if it makes the chip cost a few cents more. Lots of internal DRAM too.

Lift some limits that seem to be artificial, like the LED-PWM module that only has 14 bit timers (but four of them...?). I don't think it would be such a big deal to have two of them and then have them 16 bit or even better 20 bit.

[mikemoy]

t would you like to see in The Next Chip?

Dont want to see the next chip. Want to see the P4

[MicroController]

A chip based on the "new" ARM processor cores but ...

I think you may want to edit that post

[eriksl]

No I am not going to edit, I will just take all the mocking laughter, which I truly deserve here. What a capital stupid mistake! It might be some wishful thinking there.

So of course I meant "RISC-V".

BTW I do understand that RISC-V cores are much cheaper than ARM (due to IP), but ARM is getting more and more the de facto standard in industry.

[Sprite]

BTW I do understand that RISC-V cores are much cheaper than ARM (due to IP), but ARM is getting more and more the de facto standard in industry.

I think that can be debated. In general computing? Sure, with Apple moving to Arm, Qualcomm trying to make inroads to run Windows etc, you could make that point. For embedded microcontrollers, I feel it's going the other way. There still are the usual suspects who run Arm, but some manufacturers certainly are going the other way as well.

[eriksl]

OK, clear. In my area of interest I'm only seeing ARM now, but those are more like complex SoC's for running STB's etc.

Anyway, so, yeah, very curious about a best of both worlds from the 'C' and 'S' series.

[Baldhead]

Suggestion for improvement:

I don't know if any Espressif microcontroller already implements this.
As far as I know esp32-s3 does not implement it.

Sshadow registers / Banked registers:
"In technical literature, hardware registers that automatically save the interrupt context are most commonly referred to as shadow registers or banked registers.
These are duplicate sets of general-purpose registers that are switched in automatically by the hardware upon an interrupt, allowing the processor's state to be saved quickly without explicit push/pop operations to the stack".

And they must have more than one set of these registers per CPU core.

The interrupt latency without these registers is very high.